<"asictable:cell", Hidden = yes> <"asictable:cell", Hidden = yes> <"asictable:cell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:cell", Hidden = yes> <"asictable:cell", Hidden = yes> <"asictable:cell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:bitcell", Hidden = yes> <"asictable:cell", Font = F11@Z7@Lam,Alignment = Center> MXDX48 IC Memory Map <"asictable:cell", Font = F3@Z7@Lam,Alignment = Center> (created on Thu Apr 15 09:20:53 199 by parse_rdf from t.rdf) <"asictable:bitcell", Font = F9@Z7@Lam> Hex <"asictable:cell"> <"asictable:cell"> <"asictable:cell", Font = F9@Z7@Lam,Alignment = Center> Data Bits <"asictable:bitcell", Font = F9@Z7@Lam> Offset <"asictable:cell", Font = F9@Z7@Lam,Alignment = Center> Description <"asictable:bitcell", Font = F9@Z7@Lam,Alignment = Center> Access <"asictable:bitcell", Font = F7@Z7@Lam> 16 <"asictable:bitcell", Font = F7@Z7@Lam> 15 <"asictable:bitcell", Font = F7@Z7@Lam> 14 <"asictable:bitcell", Font = F7@Z7@Lam> 13 <"asictable:bitcell", Font = F7@Z7@Lam> 12 <"asictable:bitcell", Font = F7@Z7@Lam> 11 <"asictable:bitcell", Font = F7@Z7@Lam> 10 <"asictable:bitcell", Font = F7@Z7@Lam> 9 <"asictable:bitcell", Font = F7@Z7@Lam> 8 <"asictable:bitcell", Font = F7@Z7@Lam> 7 <"asictable:bitcell", Font = F7@Z7@Lam> 6 <"asictable:bitcell", Font = F7@Z7@Lam> 5 <"asictable:bitcell", Font = F7@Z7@Lam> 4 <"asictable:bitcell", Font = F7@Z7@Lam> 3 <"asictable:bitcell", Font = F7@Z7@Lam> 2 <"asictable:bitcell", Font = F7@Z7@Lam> 1 <|,"2"> <"asictable:cell", Font = F11@Z7@Lam> 0000-001C UPINTF General Block <"asictable:cell", Font = F9@Z7@Lam,Alignment = Center> 002 <"asictable:cell", Font = F2@Z7@Lam> Master Alarm Summary Mask <"asictable:cell", Font = F2@Z7@Lam> rd/wr <"asictable:bitcell"> --- <"asictable:bitcell"> --- <"asictable:bitcell"> --- <"asictable:bitcell"> --- <"asictable:bitcell"> --- <"asictable:bitcell"> Geni <"asictable:bitcell"> J0 c <"asictable:bitcell"> RX C <"asictable:bitcell"> IB T <"asictable:bitcell"> OOB <"asictable:bitcell"> Sync <"asictable:bitcell"> RX P <"asictable:bitcell"> RX L <"asictable:bitcell"> RX F <"asictable:bitcell"> Cloc <"asictable:bitcell"> Glob <|,"2"> <"asictable:cell"> <"asictable:bitcell", Font = F8@Z7@Lam> 15-11
10
9
8
7
6
5
4
3
2
1
0 <"asictable:cell", Font = F8@Z7@Lam>
Genin chg Alm Mask
J0 chg Alm Mask
RX CCIMM Alm Sum Mask
IB TX GBI Alm Sum. Mask
OOB TX GBI Alm Sum. Mask
Sync Alarm Summary Mask
RX Path PM Summary Mask
RX Line PM Summary Mask
RX Framer/Descra Mask
Clock Alarm Mask
Global Int* Mask <"asictable:bitcell", Font = F8@Z7@Lam> <"asictable:cell", Font = F8@Z7@Lam> Unused
1 = Mask corresponding Alarm in Master Alarm Summary Reg.









hmm