:ASIC:SAMP :REG_WIDTH: 16 :BLOCK: //BLK# 1stAdr LastAdr Abbrev Descriptive Name 0 0x0000 0x003e GLOB Global Provisioning and Status 1 0x0040 0x00fe STRO STAR Output Provisioning 2 0x0100 0x013e TMG Timing Provisioning and Status 3 0x0140 0x01fe STRI STAR Input Provisioning and Status 4 0x0200 0x023e STSI Payload Input Provisioning and Status 5 0x0240 0x027e STSO Payload Output Provisioning and Status 6 0x0280 0x02fe STSPM STS Performance Monitoring Provisioning and Status 7 0x0300 0x03fe VTPP VT Pointer Processor Provisioning and Status 8 0x0400 0x06fe VTINT VT Performance Monitoring Interrupt Status 9 0x0700 0x09fe VTMSK VT Performance Monitoring Interrupt Mask 10 0x0a00 0x0cfe VTPM2 VT Performance Monitoring BIP2 Accumulation 11 0x0d00 0x0d3e VTTHSH VT Performance Monitoring BIP Threshold Prov 12 0x0d40 0x0d9e VTSUM VT Performance Monitoring Alarm Summary 13 0x0da0 0x0dce VTRDI VT Performance Monitoring RDI 14 0x0dd0 0x0dfe VTRFI VT Performance Monitoring RFI 15 0x0e00 0x0e2e VTAIS VT Performance Monitoring AIS/LOP Summary :BLOCK_END: :REG : Clock Sel Interrupt :abrv: CLKINT :ADDR: 0x000 GLOB :RWCI: c/i :mask: 0x002 GLOB :MSB LSB NibName Description 3 OSF2 1 = Other Side 2 kHz Sync Fail (Distributed Clock) 2 TSF2 1 = This Side 2 kHz Sync Fail (From Clock PBA) 1 OSF6 1 = Other Side 6.48M Clock Fail (Distributed Clock) 0 TSF6 1 = This Side 6.48M Clock Fail (From Clock PBA) :hini: :aini: :sini: :cmnt: :REG_END: :REG : Clock Select Int Mask :abrv: CLKMSK :ADDR: 0x002 GLOB :RWCI: r/w :mask: :MSB LSB NibName Description 3 OSF2 1 = Mask Other Side 2 kHz Sync Fail Interrupt 2 TSF2 1 = Mask This Side 2 kHz Sync Fail Interrupt 1 OSF6 1 = Mask Other Side 6.48M Clock Fail Interrupt 0 TSF6 1 = Mask This Side 6.48M Clock Fail Interrupt :hini: :aini: :sini: :cmnt: :REG_END: :REG : STAR I/F Interrupt Summary :abrv: STRINT :ADDR: 0x004 GLOB :RWCI: r/i :mask: 0x002 GLOB :MSB LSB NibName Description 2 STR3 1 = Interrupt active Star I/F 3 ::0x098 STRI:: 1 STR2 1 = Interrupt active Star I/F 2 ::0x058 STRI:: 0 STR1 1 = Interrupt active Star I/F 1 ::0x018 STRI:: :hini: :aini: :sini: :cmnt: :REG_END: :REG : STAR I/F Summary Mask :abrv: STRMSK :ADDR: 0x006 GLOB :RWCI: r/w :mask: :MSB LSB NibName Description 2 STR3 1 = Mask Interrupt Star I/F 3 1 STR2 1 = Mask Interrupt Star I/F 2 0 STR1 1 = Mask Interrupt Star I/F 1 :hini: :aini: :sini: :cmnt: :REG_END: :REG : Master Interrupt Summary :abrv: MSTINT :ADDR: 0x008 GLOB :RWCI: r/i :mask: 0x00a GLOB :MSB LSB NibName Description 8 GENI 1 = Generic input Change, Reg ::0x1e GLOB:: 7 IBP 1 = STS Input Inband Parity Error, Reg ::0x20 STSI:: 6 VTC 1 = VT PPS Int (Block C) Regs ::0x8 VTSUM:: ::0xa VTSUM:: ::0x8 VTAIS:: ::0xa VTAIS:: 5 VTB 1 = VT PPS Int (Block B) Regs ::0x4 VTSUM:: ::0x6 VTSUM:: ::0x4 VTAIS:: ::0x6 VTAIS:: 4 VTA 1 = VT PPS Int (Block A) Regs ::0x0 VTSUM:: ::0x2 VTSUM:: ::0x0 VTAIS:: ::0x2 VTAIS:: 3 VTMF 1 = VT Multiframe Loss Int Regs ::0x10 VTPP:: 2 STS 1 = STS PPS Int Regs ::0x10 STSPM:: ::0x14 STSPM:: 1 STR 1 = STAR I/F Int Reg ::0x04 GLOB:: 0 TIM 1 = Timing Int Reg ::0x02 TMG:: & Clock Sel Int Reg ::0x00 GLOB:: :hini: :aini: :sini: :cmnt: Bit 7 & 8 new for SAMP :REG_END: :REG : Master Interrupt Mask :abrv: MSTMSK :ADDR: 0x00a GLOB :RWCI: r/w :mask: :MSB LSB NibName Description 8 GENI 1 = Mask GENI Int 7 IBP 1 = Mask STS Input Inband Parity Error 6 VTC 1 = Mask VT PPS Int (Block C) 5 VTB 1 = Mask VT PPS Int (Block B) 4 VTA 1 = Mask VT PPS Int (Block A) 3 VTMF 1 = Mask VT Multiframe Loss Int 2 STS 1 = Mask STS PPS Int 1 STR 1 = Mask STAR I/F Int 0 TIM 1 = Mask Timing Int & Clock Sel Int :hini: :aini: :sini: :cmnt: Bit 7 & 8 new for SAMP :REG_END: :REG : UCFAIL & POR :abrv: UCFPOR :ADDR: 0x00c GLOB :RWCI: r/w :mask: :MSB LSB NibName Description 7 STR8 1 = Disable STROUT8 for backup clock distribution (HIF/LIF Use) 6 5 BP 11 = Bypass PLL clock <6>51.84M, <5>155.52M, Normal = 00 4 3 PLL1 PLLRANGE, Normal = 11 for 155.52 MHz PLL operation PLL0 00 for 51.84 MHz PLL operation (no clock recovery) 2 PLLRST 1 = Reset PLL on POR* or write (write to 0 to enable PLL) 1 UCF UCFAIL, set to 1 when async UCFAIL event occurs, write 0 to clear 0 POR Power-On-Reset, set to 1 when async POR event occurs, must be written to 0 to clear event. :hini: :aini: :sini: :cmnt: :REG_END: :REG : Clock Select Status :abrv: CLKSTAT :ADDR: 0x00e GLOB :RWCI: r :mask: :MSB LSB NibName Description 0 OSST Other Side Clock Auto Select Status 0 = This Side, 1 = Other Side :hini: :aini: :sini: :cmnt: :REG_END: :REG : Global Provisioning :abrv: GBPPROV :ADDR: 0x010 GLOB :RWCI: r/w :mask: :MSB LSB NibName Description 2 ACRD Side provisioning (whoami), used i hardware auto-squelching 1 = ACARD, 0 = BCARD 1 STSD STS Monitor Direction. Sets datapath direction for the STS rings monitoring functions. 0 = */** output direction (To backplane) HIF mode 1 = */** input direction (From backplane)VSCC mode 0 VTD VT Monitor Direction. Sets datapath direction for the VT Pointer Processor and VT rings monitoring functions 0 = */** output direction (To backplane) HIF mode 1 = */** input direction (From backplane)VSCC mode :hini: :aini: :sini: :cmnt: :REG_END: :REG : Test Provisioning :abrv: TSTPRV :ADDR: 0x012 GLOB :RWCI: r/w :mask: :MSB LSB NibName Description 15 2 Unspec Unspecified 1 0 FCT Fast Count Test Mode 11 Reserved 10 Row 0-8, Col 0-4 01 Row 0-4, Col 0-3 (E2 mapped to C1) 00 Normal Row 0-8, Col 0-89 :hini: :aini: :sini: :cmnt: :REG_END: :REG : Clock Select Provisioning :abrv: CLKPRV :ADDR: 0x014 GLOB :RWCI: r/w :mask: :MSB LSB NibName Description 5 ASEL Other Side Distributed Clock Select, 1 = A Side, 0 = B Side 4 ATEN Auto Select Enable, 1 = enabled 3 OSSL Side Select, 1 = Other Side, 0 = This Side 2 TST Test Mode, 1 = Test Mode, 0 = Normal Mode 1 FOS Force Other Side if OS clock is good 0 FTS Force This Side if TS clock is good :hini: :aini: :sini: :cmnt: :REG_END: :REG : Diagnostic Register :abrv: DIAG :ADDR: 0x016 GLOB :RWCI: r/w :mask: :MSB LSB NibName Description 15 0 D Read/Write register for uP intf diagnostics, no internal function :hini: :aini: :sini: :cmnt: :REG_END: :REG : Device Type & ID :abrv: DEVID :ADDR: 0x018 GLOB :RWCI: r :mask: :MSB LSB NibName Description 15 8 REV Revision Field, Fixed to '00' hex for SAMP rev 1 7 0 ID Device ID field, Fixed to '00100111'b, 27 hex, 39 Decimal :hini: :aini: :sini: :cmnt: :REG_END: :REG : Generic I/O Control :abrv: GENIO :ADDR: 0x01a GLOB :RWCI: r/w :mask: :MSB LSB NibName Description 7 4 GENIOH Controls output pins GENIOH[3:0] (POR sets to 1) 3 0 GENIOL Controls output pins GENIOL[3:0] (POR sets to 0) :hini: :aini: :sini: :cmnt: (New for SAMP) Value written to this register appears on output pin :REG_END: :REG : Extraneous Pin State Reflections :abrv: EXPINS :ADDR: 0x01c GLOB :RWCI: r :mask: :MSB LSB NibName Description 7 EPH External Pin H = SCANTST, Normally 0 6 EPG External Pin G = POR* (unlatched) 5 EPF External Pin F = Internal INT* 4 EPE External Pins E-A = TSTMODE<4..0>, Normally 00000 3 EPD 2 EPC 1 EPB 0 EPA :hini: :aini: :sini: :cmnt: New for SAMP. Was bits 15 - 8 of reg ::0x18 GLOB:: in VTPP :REG_END: :REG : Generic Input Change :abrv: GENICHG :ADDR: 0x1e GLOB :RWCI: c/i :mask: 0x20 GLOB :MSB LSB NibName Description 7 0 GENICHG 1 = Change on GENI Input pin :hini: :aini: :sini: :cmnt: (New for SAMP) :REG_END: :REG : Generic Input Mask :abrv: GENIMSK :ADDR: 0x20 GLOB :RWCI: r/w :mask: :MSB LSB NibName Description 7 0 GENI 1 = Mask Change Interrupt :hini: :aini: :sini: :cmnt: (New for SAMP) :REG_END: :REG : Generic Input Status :abrv: GENISTAT :ADDR: 0x22 GLOB :RWCI: r :mask: :MSB LSB NibName Description 7 0 GENI Reflects state of GENI input pins :hini: :aini: :sini: :cmnt: (New for SAMP) :REG_END: // Star Interface Blocks // STAR OUT DPI :REG : Star Out Mode2 (Gp # 1) :abrv: MD2GP1 :ADDR: 0x0 STRO :RWCI: r/w :MSB LSB NibName Description 6 ENLT 1 = Enable insertion of LTALK Bytes D1* & D2* 5 SQEN 1 = Enable Auto Hardware Squelch to insert all 1's except Star bytes 4 SWSQ Software Force Squelch Control, 1 = squelch 3 SYNA Sync Enable A, 1 = enable sync distribution on A outputs 2 SYNB Sync Enable B, 1 = enable sync distribution on B outputs 1 RFMD Reference Mode *bit-5, 0 = 51.84 MHz Anti-phase, 1 = 6.48 MHz 0 PSDS Pseudo Random Data Select, 1 = select PSR data, 0 = Normal Data :cmnt: Bit 6 new for SAMP :hini: 0x02 :aini: 0x0e :REG_END: :REG : Star Out Mode1 (Gp # 1) :abrv: MD1GP1 :ADDR: 0x2 STRO :RWCI: r/w :MSB LSB NibName Description 7 4 AIS<4:1> AIS Insert, 1 = insert all ones with good star mode bytes AIS<4> controls STS<4>, AIS<3>-STS<3>, AIS<2>-STS<2>, AIS<1>-STS<1> 3 AEN A Side Enable, 1 = default/enable, 0 = force all 1's 2 BEN B Side Enable, 1 = default/enable, 0 = force all 1's 1 A* Star Mode, A Side, 1 = * mode, 0 = ** mode 0 B* Star Mode, B Side, 1 = * mode, 0 = ** mode2 :hini: 0x0c :aini: 0x0f :REG_END: :REG : Output E2* Byte (Gp # 1) :abrv: E2GP1 :ADDR: 0x4 STRO :RWCI: r/w :MSB LSB NibName Description 7 0 E2*<7:0> E2* output byte :hini: 0xe2 :aini: 0x00 :REG_END: :REG : Output K2* Byte (Gp # 1) :abrv: K2GP1 :ADDR: 0x6 STRO :RWCI: r/w :MSB LSB NibName Description 7 0 K2*<7:0> K2* output byte :hini: 0xc1 :aini: 0x00 :REG_END: :REG : Output K1* Byte (Gp # 1) :abrv: K1GP1 :ADDR: 0x8 STRO :RWCI: r/w :MSB LSB NibName Description 7 0 K1*<7:0> K1* output byte :hini: 0xc1 :aini: 0x00 :REG_END: :REG : Output D2* Byte (Gp # 1) :abrv: D2GP1 :ADDR: 0xa STRO :RWCI: r/w :MSB LSB NibName Description 7 0 D2*<7:0> D2* output byte :hini: 0xd2 :aini: 0x00 :cmnt: New for SAMP :REG_END: :REG : Output D1* Byte (Gp # 1) :abrv: D1GP1 :ADDR: 0xc STRO :RWCI: r/w :MSB LSB NibName Description 7 0 D1*<7:0> D1* output byte :hini: 0xd2 :aini: 0x00 :cmnt: New for SAMP :REG_END: :REG : Star Out Mode2 (Gp # 2) :abrv: MD2GP2 :ADDR: 0x040 STRO :same: 0x000 STRO :REG_END: :REG : Star Out Mode1 (Gp # 2) :abrv: MD1GP2 :ADDR: 0x042 STRO :same: 0x002 STRO :REG_END: :REG : Star Out E2* Byte (Gp # 2) :abrv: E2GP2 :ADDR: 0x044 STRO :same: 0x004 STRO :REG_END: :REG : Star Out K2* Byte (Gp # 2) :abrv: K2GP2 :ADDR: 0x046 STRO :same: 0x006 STRO :REG_END: :REG : Star Out K1* Byte (Gp # 2) :abrv: K1GP2 :ADDR: 0x048 STRO :same: 0x008 STRO :REG_END: :REG : Output D2* Byte (Gp # 2) :abrv: D2GP2 :ADDR: 0x4a STRO :RWCI: r/w :MSB LSB NibName Description 7 0 D2*<7:0> D2* output byte :hini: 0xd2 :aini: 0x00 :cmnt: New for SAMP :REG_END: :REG : Output D1* Byte (Gp # 2) :abrv: D1GP2 :ADDR: 0x4c STRO :RWCI: r/w :MSB LSB NibName Description 7 0 D1*<7:0> D1* output byte :hini: 0xd2 :aini: 0x00 :cmnt: New for SAMP :REG_END: :REG : Star Out Mode2 (Gp # 3) :abrv: MD2GP3 :ADDR: 0x080 STRO :same: 0x000 STRO :REG_END: :REG : Star Out Mode1 (Gp # 3) :abrv: MD1GP3 :ADDR: 0x082 STRO :same: 0x002 STRO :REG_END: :REG : Star Out E2* Byte (Gp # 3) :abrv: E2GP3 :ADDR: 0x084 STRO :same: 0x004 STRO :REG_END: :REG : Star Out K2* Byte (Gp # 3) :abrv: K2GP3 :ADDR: 0x086 STRO :same: 0x006 STRO :REG_END: :REG : Star Out K1* Byte (Gp # 3) :abrv: K1GP3 :ADDR: 0x088 STRO :same: 0x008 STRO :REG_END: :REG : Output D2* Byte (Gp # 3) :abrv: D2GP3 :ADDR: 0x8a STRO :RWCI: r/w :MSB LSB NibName Description 7 0 D2*<7:0> D2* output byte :hini: 0xd2 :aini: 0x00 :cmnt: New for SAMP :REG_END: :REG : Output D1* Byte (Gp # 3) :abrv: D1GP3 :ADDR: 0x8c STRO :RWCI: r/w :MSB LSB NibName Description 7 0 D1*<7:0> D1* output byte :hini: 0xd2 :aini: 0x00 :cmnt: New for SAMP :REG_END: // TIMING DPI :REG : Timing Window Status :abrv: WINSTAT :ADDR: 0x000 TMG :RWCI: r :mask: :MSB LSB NibName Description 3 0 WND<3:0> Window Status Count :hini: :aini: :sini: :cmnt: Hardware Diagnostics :REG_END: :REG : Timing Interrupt Reg :abrv: TMGINT :ADDR: 0x2 TMG :RWCI: c/i :mask: 0x4 TMG :MSB LSB NibName Description 4 C32M 1 = 32.768 MHz Clock Fail 3 C51M 1 = 51.84M Fail 51.84 MHz PLL Clock Fail 2 C6M 1 = 6.48M Fail Selected 6.48 MHz Clock Fail 1 SY51 1 = MstSy Fail Rx Sync Fail, 51M-2kHz Ref 0 SY6 1 = SelSy Fail Rx Sync Fail, Selected 6M-2kHz Ref :cmnt: :REG_END: :REG : Timing Int Mask Reg :abrv: Tmg Mask :ADDR: 0x4 TMG :RWCI: r/w :MSB LSB NibName Description 4 M32M 1 = Mask 32M Fail 3 M51M 1 = Mask 51M Fail 51.84 MHz Clock Fail 2 M6M 1 = Mask 6M Fail 6.48 MHz Clock Fail 1 MSY51 1 = Mask MstSy Fail Rx Sync Fail, 51M-2kHz Ref 0 MSY6 1 = Mask SelSy Fail Rx Sync Fail, Selected 6M-2kHz Ref :aini: 0x00 :hini: 0x00 :cmnt: For Interrupt Mask Bits, 1 = mask enabled :REG_END: :REG : Timing Provisioning :abrv: Tmg Prov :ADDR: 0x6 TMG :RWCI: r/w :MSB LSB NibName Description 4 3 ESC<1:0> Elastic Store Check Size, 00=15-bit, 01=13-bit, 10=11-bit, 11=9-bit 2 VSCC 1 = VSCC mode, 0 = HIF/LIF mode 1 MST Master Mode Enable, 1 = enabled 0 WIN Window Mode Enable, 1 = enabled :hini: :aini: :REG_END: :REG : Timing Offset S1 Lower :abrv: OS1L :ADDR: 0x8 TMG :RWCI: r/w :MSB LSB NibName Description 12 0 S1<12:0> Sync1 Offset sync value :hini: 0x00 :aini: 0x00 :cmnt: Input GMF sync offset value (0 to 194f hex) S1 is Star-In offset :REG_END: :REG : Timing Offset S1 Upper :abrv: OS1U :ADDR: 0xa TMG :RWCI: r/w :MSB LSB NibName Description 1 0 S1<14:13> Sync1 Offset Multi-Frame value (0 to 3) :hini: 0x00 :aini: 0x00 :REG_END: :REG : Timing Offset S2 Lower :abrv: OS2L :ADDR: 0xc TMG :RWCI: r/w :MSB LSB NibName Description 12 0 S2<12:0> Sync2 Offset sync value :hini: 0x00 :aini: 0x00 :cmnt: VT Mode GMF sync offset value (0 to 194f hex) S2 is KTCHNSYN Output offset :REG_END: :REG : Timing Offset S2 Upper :abrv: OS2U :ADDR: 0xe TMG :RWCI: r/w :MSB LSB NibName Description 1 0 S2<14:13> Sync2 Offset Multi-Frame value (0 to 3) :hini: 0x00 :aini: 0x00 :REG_END: :REG : Timing Offset S3 Lower :abrv: OS3L :ADDR: 0x010 TMG :RWCI: r/w :MSB LSB NibName Description 12 0 S3<12:0> Sync3 Offset sync value :hini: 0x00 :aini: 0x00 :cmnt: Auxilliary GMF sync offset value (0 to 194f hex) S3 is AUXSYNC Output offset :REG_END: :REG : Timing Offset S3 Upper :abrv: OS3U :ADDR: 0x012 TMG :RWCI: r/w :MSB LSB NibName Description 1 0 S3<14:13> Sync3 Offset Multi-Frame value (0 to 3) :hini: 0x00 :aini: 0x00 :REG_END: :REG : Parallel Offset S4 :abrv: PAROS :ADDR: 0x14 TMG :RWCI: r/w :MSB LSB NibName Description 9 0 PAR Parallel Offset4 sync value (0 to 3240 dec) :hini: 0x08 :aini: 0x02 :REG_END: // STAR IN DPI // Star Interface input Group 1 :REG : Input K1* byte, A-side (Gp 1) :abrv: IN1K1A :ADDR: 0x0 STRI :RWCI: r :MSB LSB NibName Description 7 0 K1*<7:0> K1* input byte, A-side :aini: 0x00 :REG_END: :REG : Input K2* byte, A-side (Gp 1) :abrv: IN1K2A :ADDR: 0x2 STRI :RWCI: r :MSB LSB NibName Description 7 0 K2*<7:0> K2* input byte, A-side :aini: 0xff :REG_END: :REG : Input E2* byte, A-side (Gp 1) :abrv: IN1E2A :ADDR: 0x4 STRI :RWCI: r :MSB LSB NibName Description 7 0 E2*<7:0> E2* input byte, A-side :aini: 0x00 :REG_END: :REG : Input K1* byte, B-side (Gp 1) :abrv: IN1K1B :ADDR: 0x6 STRI :RWCI: r :MSB LSB NibName Description 7 0 K1*<7:0> K1* input byte, B-side :aini: 0x00 :REG_END: :REG : Input K2* byte, B-side (Gp 1) :abrv: IN1K2B :ADDR: 0x8 STRI :RWCI: r :MSB LSB NibName Description 7 0 K2*<7:0> K2* input byte, B-side :aini: 0xff :REG_END: :REG : Input E2* byte, B-side (Gp 1) :abrv: IN1E2B :ADDR: 0xa STRI :RWCI: r :MSB LSB NibName Description 7 0 E2*<7:0> E2* input byte, B-side :aini: 0x00 :REG_END: :REG : Star In Status (Gp 1) :abrv: IN1STAT :ADDR: 0xc STRI :RWCI: c :MSB LSB NibName Description 4 ESST Elastic Store Error, 1 = Alignment Error 3 A1B A1A2 Mismatch Error B side, 1 = Single error 2 A1A A1A2 Mismatch Error A side, 1 = Single error 1 ERRB B2 Error on B side, 1 = Single error 0 ERRA B2 Error on A side, 1 = Single error :aini: :REG_END: :REG : Star In A side Int1 (Gp 1) :abrv: IN1AALM1 :ADDR: 0xe STRI :RWCI: c :MSB LSB NibName Description 1 LORF * Mode, 1 = 6 MHz phase reference failure, A side ** Mode, */** status, 1 = ** mode, 0 = * mode 0 LOSY 1 = Star Mode Sync Input failure, A side :aini: 0x01 :cmnt: Mask during ** mode. */** status indicator. All bits masked by bit<0>, Star In Interrupt Mask register ::0x18 STRI::. :REG_END: :REG : Star In B side Int1 (Gp 1) :abrv: IN1BALM1 :ADDR: 0x10 STRI :RWCI: c :MSB LSB NibName Description 1 LORF * Mode, 1 = 6 MHz phase reference failure, B side ** Mode, */** status, 1 = ** mode, 0 = * mode 0 LOSY 1 = Star Mode Sync Input failure, B side :aini: 0x01 :cmnt: Mask during ** mode. */** status indicator. All bits masked by bit<1>, Star In Interrupt Mask register ::0x18 STRI::. :REG_END: :REG : Star In A side Int2 (Gp 1) :abrv: IN1AALM2 :ADDR: 0x12 STRI :RWCI: c :MSB LSB NibName Description 2 FAIL Star Data Fail A side, 1 = B2* error threshold exceded 1 K2CH K2* byte change A side, 1 = change 0 K1CH K1* byte change A side, 1 = change :aini: 0x03 :cmnt: All bits masked by bit<2>, Star In Interrupt Mask register ::0x18 STRI::. :REG_END: :REG : Star In B side Int2 (Gp 1) :abrv: IN1BALM2 :ADDR: 0x14 STRI :RWCI: c :MSB LSB NibName Description 2 FAIL Star Data Fail B side, 1 = B2* error threshold exceded 1 K2CH K2* byte change B side, 1 = change 0 K1CH K1* byte change B side, 1 = change :aini: 0x03 :cmnt: All bits masked by bit<3>, Star In Interrupt Mask register ::0x18 STRI::. :REG_END: :REG : Star In Int Mask (Gp 1) :abrv: IN1MSK :ADDR: 0x16 STRI :RWCI: r/w :MSB LSB NibName Description 4 M3 1 = Mask interrupt from D1/D2 change 3 M2B 1 = Mask interrupt from In B Int2 2 M2A 1 = Mask interrupt from In A Int2 1 M1B 1 = Mask interrupt from In B Int1 0 M1A 1 = Mask interrupt from In A Int1 :hini: 0x00 :aini: 0x00 :cmnt: (Bit 4 new for SAMP) Masks Star Input Interrupt Summary register. :REG_END: :REG : Star In Int Summary (Gp 1) :abrv: IN1SUM :ADDR: 0x18 STRI :RWCI: r/i :mask: 0x16 STRI :MSB LSB NibName Description 4 I3 Summary bit for D1/D2 chg, 1 = Interrupt Active in reg ::0x28 STRI:: 3 I2B Summary bit for In B Int2, 1 = Interrupt Active in reg ::0x14 STRI:: 2 I2A Summary bit for In A Int2, 1 = Interrupt Active in reg ::0x12 STRI:: 1 I1B Summary bit for In B Int1, 1 = Interrupt Active in reg ::0x10 STRI:: 0 I1A Summary bit for In A Int1, 1 = Interrupt Active in reg ::0x0e STRI:: :cmnt: (Bit 4 new for SAMP) Bits masked by Star Input Interrupt Mask register are NOT read. :REG_END: :REG : Input Star Mode (Gp 1) :abrv: IN1STRMD :ADDR: 0x1a STRI :RWCI: r/w :MSB LSB NibName Description 3 2 SEL<1:0> 11 - Insert all 1's to all links 10 - Enable Star Out to Star In Loop 01 - Select A Side Input 00 - Select B Side Input 1 B* Star Mode, B Side, 1 = *mode, 0 = **mode 0 A* Star Mode, A Side, 1 = *mode, 0 = **mode :hini: 0x07 :aini: 0x07 :REG_END: :REG : Input Prov (Gp 1) :abrv: IN1PROV :ADDR: 0x1c STRI :RWCI: r/w :MSB LSB NibName Description 2 AUXEN 1 = Enable Star In group 1 to use sync and ref from group 2 1 B2EN 1 = Enable hardware AIS Insert upon B2* Fail or Loss-of-Ref, 1 = normal / enable 0 CRBP Clock Recovery Bypass (reference mode for STRIN bit-5) 1 = bypass = 51.84 MHz anti-phase mode 0 = normal = 6.48 MHz reference mode :hini: 0x06 :aini: 0x00 :cmnt: Bit 2 (New for SAMP) is for OC12 drop applications where all 3 drops get sync and ref from the Group 2 Star Bus :REG_END: :REG : Input ES Alignment (Gp 1) :abrv: IN1ESALGN :ADDR: 0x1e STRI :RWCI: r :MSB LSB NibName Description 3 0 ES<3:0> ES Align Input Elastic Store alignment position :cmnt: 5-6 is centered, C-F is near spill. Star In Status register, bit<4> detects alignment fail. :REG_END: :REG : Input D1* byte, A-side (Gp 1) :abrv: IN1D1A :ADDR: 0x20 STRI :RWCI: r :MSB LSB NibName Description 7 0 D1*<7:0> D1* input byte, A-side :aini: 0x00 :cmnt: New for SAMP :REG_END: :REG : Input D2* byte, A-side (Gp 1) :abrv: IN1D2A :ADDR: 0x22 STRI :RWCI: r :MSB LSB NibName Description 7 0 D2*<7:0> D2* input byte, A-side :aini: 0xff :cmnt: New for SAMP :REG_END: :REG : Input D1* byte, B-side (Gp 1) :abrv: IN1D1B :ADDR: 0x24 STRI :RWCI: r :MSB LSB NibName Description 7 0 D1*<7:0> D1* input byte, B-side :aini: 0x00 :cmnt: New for SAMP :REG_END: :REG : Input D2* byte, B-side (Gp 1) :abrv: IN1D2B :ADDR: 0x26 STRI :RWCI: r :MSB LSB NibName Description 7 0 D2*<7:0> D2* input byte, B-side :aini: 0xff :cmnt: New for SAMP :REG_END: :REG : Input D1/D2 Change Interrupt (Gp 1) :abrv: IN1DBC :ADDR: 0x28 STRI :RWCI: c\i :mask: 0x2a STRI :MSB LSB NibName Description 3 D1A 1 = Change in A side D1* byte 2 D2A 1 = Change in A side D2* byte 1 D1B 1 = Change in B side D1* byte 0 D2B 1 = Change in B side D2* byte :hini: :aini: :sini: :cmnt: New for SAMP :REG_END: :REG : Input D1/D2 Change Interrupt Mask (Gp 1) :abrv: IN1DBM :ADDR: 0x2a STRI :RWCI: r\w :mask: :MSB LSB NibName Description 3 D1A 1 = Mask Change in A side D1* byte 2 D2A 1 = Mask Change in A side D2* byte 1 D1B 1 = Mask Change in B side D1* byte 0 D2B 1 = Mask Change in B side D2* byte :hini: :aini: :sini: :cmnt: New for SAMP :REG_END: // Star Interface input Group 2 :REG : Input K1* byte, A-side (Gp 2) :abrv: IN2K1A :ADDR: 0x40 STRI :RWCI: r :MSB LSB NibName Description 7 0 K1*<7:0> K1* input byte, A-side :aini: 0x00 :REG_END: :REG : Input K2* byte, A-side (Gp 2) :abrv: IN2K2A :ADDR: 0x42 STRI :RWCI: r :MSB LSB NibName Description 7 0 K2*<7:0> K2* input byte, A-side :aini: 0xff :REG_END: :REG : Input E2* byte, A-side (Gp 2) :abrv: IN2E2A :ADDR: 0x44 STRI :RWCI: r :MSB LSB NibName Description 7 0 E2*<7:0> E2* input byte, A-side :aini: 0x00 :REG_END: :REG : Input K1* byte, B-side (Gp 2) :abrv: IN2K1B :ADDR: 0x46 STRI :RWCI: r :MSB LSB NibName Description 7 0 K1*<7:0> K1* input byte, B-side :aini: 0x00 :REG_END: :REG : Input K2* byte, B-side (Gp 2) :abrv: IN2K2B :ADDR: 0x48 STRI :RWCI: r :MSB LSB NibName Description 7 0 K2*<7:0> K2* input byte, B-side :aini: 0xff :REG_END: :REG : Input E2* byte, B-side (Gp 2) :abrv: IN2E2B :ADDR: 0x4a STRI :RWCI: r :MSB LSB NibName Description 7 0 E2*<7:0> E2* input byte, B-side :aini: 0x00 :REG_END: :REG : Star In Status (Gp 2) :abrv: IN2STAT :ADDR: 0x4c STRI :RWCI: c :MSB LSB NibName Description 4 ESST Elastic Store Error, 1 = Alignment Error 3 A1B A1A2 Mismatch Error B side, 1 = Single error 2 A1A A1A2 Mismatch Error A side, 1 = Single error 1 ERRB B2 Error on B side, 1 = Single error 0 ERRA B2 Error on A side, 1 = Single error :aini: :REG_END: :REG : Star In A side Int1 (Gp 2) :abrv: IN2AALM1 :ADDR: 0x4e STRI :RWCI: c :MSB LSB NibName Description 1 LORF * Mode, 1 = 6 MHz phase reference failure, A side ** Mode, */** status, 1 = ** mode, 0 = * mode 0 LOSY 1 = Star Mode Sync Input failure, A side :aini: 0x01 :cmnt: Mask during ** mode. */** status indicator. All bits masked by bit<0>, Star In Interrupt Mask register ::0x58 STRI::. :REG_END: :REG : Star In B side Int1 (Gp 2) :abrv: IN2BALM1 :ADDR: 0x50 STRI :RWCI: c :MSB LSB NibName Description 1 LORF * Mode, 1 = 6 MHz phase reference failure, B side ** Mode, */** status, 1 = ** mode, 0 = * mode 0 LOSY 1 = Star Mode Sync Input failure, B side :aini: 0x01 :cmnt: Mask during ** mode. */** status indicator. All bits masked by bit<1>, Star In Interrupt Mask register ::0x58 STRI::. :REG_END: :REG : Star In A side Int2 (Gp 2) :abrv: IN2AALM2 :ADDR: 0x52 STRI :RWCI: c :MSB LSB NibName Description 2 FAIL Star Data Fail A side, 1 = B2* error threshold exceded 1 K2CH K2* byte change A side, 1 = change 0 K1CH K1* byte change A side, 1 = change :aini: 0x03 :cmnt: All bits masked by bit<2>, Star In Interrupt Mask register ::0x58 STRI::. :REG_END: :REG : Star In B side Int2 (Gp 2) :abrv: IN2BALM2 :ADDR: 0x54 STRI :RWCI: c :MSB LSB NibName Description 2 FAIL Star Data Fail B side, 1 = B2* error threshold exceded 1 K2CH K2* byte change B side, 1 = change 0 K1CH K1* byte change B side, 1 = change :aini: 0x03 :cmnt: All bits masked by bit<3>, Star In Interrupt Mask register ::0x58 STRI::. :REG_END: :REG : Star In Int Mask (Gp 2) :abrv: IN2MSK :ADDR: 0x56 STRI :RWCI: r/w :MSB LSB NibName Description 4 M3 1 = Mask interrupt from D1/D2 change 3 M2B 1 = Mask interrupt from In B Int2 2 M2A 1 = Mask interrupt from In A Int2 1 M1B 1 = Mask interrupt from In B Int1 0 M1A 1 = Mask interrupt from In A Int1 :hini: 0x00 :aini: 0x00 :cmnt: Bit 4 new for SAMP. Masks Star Input Interrupt Summary register. :REG_END: :REG : Star In Int Summary (Gp 2) :abrv: IN2SUM :ADDR: 0x58 STRI :RWCI: r/i :mask: 0x56 STRI :MSB LSB NibName Description 4 I3 Summary bit for D1/D2 chg, 1 = Interrupt Active in reg ::0x68 STRI:: 3 I2B Summary bit for In B Int2, 1 = Interrupt Active in reg ::0x54 STRI:: 2 I2A Summary bit for In A Int2, 1 = Interrupt Active in reg ::0x52 STRI:: 1 I1B Summary bit for In B Int1, 1 = Interrupt Active in reg ::0x50 STRI:: 0 I1A Summary bit for In A Int1, 1 = Interrupt Active in reg ::0x4e STRI:: :cmnt: Bit 4 new for SAMP. Bits masked by Star Input Interrupt Mask register are NOT read. :REG_END: :REG : Input Star Mode (Gp 2) :abrv: IN2STRMD :ADDR: 0x5a STRI :RWCI: r/w :MSB LSB NibName Description 3 2 SEL<1:0> 11 - Insert all 1's to all links 10 - Enable Star Out to Star In Loop 01 - Select A Side Input 00 - Select B Side Input 1 B* Star Mode, B Side, 1 = *mode, 0 = **mode 0 A* Star Mode, A Side, 1 = *mode, 0 = **mode :hini: 0x07 :aini: 0x07 :REG_END: :REG : Input Prov (Gp 2) :abrv: IN2PROV :ADDR: 0x5c STRI :RWCI: r/w :MSB LSB NibName Description 2 AUXEN 1 = Enable Star In group 2 to use sync and ref from group 2 1 B2EN 1 = Enable hardware AIS Insert upon B2* Fail or Loss-of-Ref, 1 = normal / enable 0 CRBP Clock Recovery Bypass (reference mode for STRIN bit-5) 1 = bypass = 51.84 MHz anti-phase mode 0 = normal = 6.48 MHz reference mode :hini: 0x06 :aini: 0x00 :cmnt: Bit 2 (New for SAMP) will have no affect on group 2 but is duplicated from groups 1 and 3 :REG_END: :REG : Input ES Alignment (Gp 2) :abrv: IN2ESALGN :ADDR: 0x5e STRI :RWCI: r :MSB LSB NibName Description 3 0 ES<3:0> ES Align Input Elastic Store alignment position :cmnt: 5-6 is centered, C-F is near spill. Star In Status register, bit<4> detects alignment fail. :REG_END: :REG : Input D1* byte, A-side (Gp 2) :abrv: IN2D1A :ADDR: 0x60 STRI :RWCI: r :MSB LSB NibName Description 7 0 D1*<7:0> D1* input byte, A-side :aini: 0x00 :cmnt: New for SAMP :REG_END: :REG : Input D2* byte, A-side (Gp 2) :abrv: IN2D2A :ADDR: 0x62 STRI :RWCI: r :MSB LSB NibName Description 7 0 D2*<7:0> D2* input byte, A-side :aini: 0xff :cmnt: New for SAMP :REG_END: :REG : Input D1* byte, B-side (Gp 2) :abrv: IN2D1B :ADDR: 0x64 STRI :RWCI: r :MSB LSB NibName Description 7 0 D1*<7:0> D1* input byte, B-side :aini: 0x00 :cmnt: New for SAMP :REG_END: :REG : Input D2* byte, B-side (Gp 2) :abrv: IN2D2B :ADDR: 0x66 STRI :RWCI: r :MSB LSB NibName Description 7 0 D2*<7:0> D2* input byte, B-side :aini: 0xff :cmnt: New for SAMP :REG_END: :REG : Input D1/D2 Change Interrupt (Gp 2) :abrv: IN2DBC :ADDR: 0x68 STRI :RWCI: c\i :mask: 0x6a STRI :MSB LSB NibName Description 3 D1A 1 = Change in A side D1* byte 2 D2A 1 = Change in A side D2* byte 1 D1B 1 = Change in B side D1* byte 0 D2B 1 = Change in B side D2* byte :hini: :aini: :sini: :cmnt: New for SAMP :REG_END: :REG : Input D1/D2 Change Interrupt Mask (Gp 2) :abrv: IN2DBM :ADDR: 0x6a STRI :RWCI: r\w :mask: :MSB LSB NibName Description 3 D1A 1 = Mask Change in A side D1* byte 2 D2A 1 = Mask Change in A side D2* byte 1 D1B 1 = Mask Change in B side D1* byte 0 D2B 1 = Mask Change in B side D2* byte :hini: :aini: :sini: :cmnt: New for SAMP :REG_END: // Star Interface input Group 3 :REG : Input K1* byte, A-side (Gp 3) :abrv: IN3K1A :ADDR: 0x80 STRI :RWCI: r :MSB LSB NibName Description 7 0 K1*<7:0> K1* input byte, A-side :aini: 0x00 :REG_END: :REG : Input K2* byte, A-side (Gp 3) :abrv: IN3K2A :ADDR: 0x82 STRI :RWCI: r :MSB LSB NibName Description 7 0 K2*<7:0> K2* input byte, A-side :aini: 0xff :REG_END: :REG : Input E2* byte, A-side (Gp 3) :abrv: IN3E2A :ADDR: 0x84 STRI :RWCI: r :MSB LSB NibName Description 7 0 E2*<7:0> E2* input byte, A-side :aini: 0x00 :REG_END: :REG : Input K1* byte, B-side (Gp 3) :abrv: IN3K1B :ADDR: 0x86 STRI :RWCI: r :MSB LSB NibName Description 7 0 K1*<7:0> K1* input byte, B-side :aini: 0x00 :REG_END: :REG : Input K2* byte, B-side (Gp 3) :abrv: IN3K2B :ADDR: 0x88 STRI :RWCI: r :MSB LSB NibName Description 7 0 K2*<7:0> K2* input byte, B-side :aini: 0xff :REG_END: :REG : Input E2* byte, B-side (Gp 3) :abrv: IN3E2B :ADDR: 0x8a STRI :RWCI: r :MSB LSB NibName Description 7 0 E2*<7:0> E2* input byte, B-side :aini: 0x00 :REG_END: :REG : Star In Status (Gp 3) :abrv: IN3STAT :ADDR: 0x8c STRI :RWCI: c :MSB LSB NibName Description 4 ESST Elastic Store Error, 1 = Alignment Error 3 A1B A1A2 Mismatch Error B side, 1 = Single error 2 A1A A1A2 Mismatch Error A side, 1 = Single error 1 ERRB B2 Error on B side, 1 = Single error 0 ERRA B2 Error on A side, 1 = Single error :aini: :REG_END: :REG : Star In A side Int1 (Gp 3) :abrv: IN3AALM1 :ADDR: 0x8e STRI :RWCI: c :MSB LSB NibName Description 1 LORF * Mode, 1 = 6 MHz phase reference failure, A side ** Mode, */** status, 1 = ** mode, 0 = * mode 0 LOSY 1 = Star Mode Sync Input failure, A side :aini: 0x01 :cmnt: Mask during ** mode. */** status indicator. All bits masked by bit<0>, Star In Interrupt Mask register ::0x98 STRI::. :REG_END: :REG : Star In B side Int1 (Gp 3) :abrv: IN3BALM1 :ADDR: 0x90 STRI :RWCI: c :MSB LSB NibName Description 1 LORF * Mode, 1 = 6 MHz phase reference failure, B side ** Mode, */** status, 1 = ** mode, 0 = * mode 0 LOSY 1 = Star Mode Sync Input failure, B side :aini: 0x01 :cmnt: Mask during ** mode. */** status indicator. All bits masked by bit<1>, Star In Interrupt Mask register ::0x98 STRI::. :REG_END: :REG : Star In A side Int2 (Gp 3) :abrv: IN3AALM2 :ADDR: 0x92 STRI :RWCI: c :MSB LSB NibName Description 2 FAIL Star Data Fail A side, 1 = B2* error threshold exceded 1 K2CH K2* byte change A side, 1 = change 0 K1CH K1* byte change A side, 1 = change :aini: 0x03 :cmnt: All bits masked by bit<2>, Star In Interrupt Mask register ::0x98 STRI::. :REG_END: :REG : Star In B side Int2 (Gp 3) :abrv: IN3BALM2 :ADDR: 0x94 STRI :RWCI: c :MSB LSB NibName Description 2 FAIL Star Data Fail B side, 1 = B2* error threshold exceded 1 K2CH K2* byte change B side, 1 = change 0 K1CH K1* byte change B side, 1 = change :aini: 0x03 :cmnt: All bits masked by bit<3>, Star In Interrupt Mask register ::0x98 STRI::. :REG_END: :REG : Star In Int Mask (Gp 3) :abrv: IN3MSK :ADDR: 0x96 STRI :RWCI: r/w :MSB LSB NibName Description 4 M3 1 = Mask interrupt from D1/D2 change 3 M2B 1 = Mask interrupt from In B Int2 2 M2A 1 = Mask interrupt from In A Int2 1 M1B 1 = Mask interrupt from In B Int1 0 M1A 1 = Mask interrupt from In A Int1 :hini: 0x00 :aini: 0x00 :cmnt: Bit 4 new for SAMP. Masks Star Input Interrupt Summary register. :REG_END: :REG : Star In Int Summary (Gp 3) :abrv: IN3SUM :ADDR: 0x98 STRI :RWCI: r/i :mask: 0x96 STRI :MSB LSB NibName Description 4 I3 Summary bit for D1/D2 chg, 1 = Interrupt Active in reg ::0xa8 STRI:: 3 I2B Summary bit for In B Int2, 1 = Interrupt Active in reg ::0x94 STRI:: 2 I2A Summary bit for In A Int2, 1 = Interrupt Active in reg ::0x92 STRI:: 1 I1B Summary bit for In B Int1, 1 = Interrupt Active in reg ::0x90 STRI:: 0 I1A Summary bit for In A Int1, 1 = Interrupt Active in reg ::0x8e STRI:: :cmnt: Bit 4 new for SAMP. Bits masked by Star Input Interrupt Mask register are NOT read. :REG_END: :REG : Input Star Mode (Gp 3) :abrv: IN3STRMD :ADDR: 0x9a STRI :RWCI: r/w :MSB LSB NibName Description 3 2 SEL<1:0> 11 - Insert all 1's to all links 10 - Enable Star Out to Star In Loop 01 - Select A Side Input 00 - Select B Side Input 1 B* Star Mode, B Side, 1 = *mode, 0 = **mode 0 A* Star Mode, A Side, 1 = *mode, 0 = **mode :hini: 0x07 :aini: 0x07 :REG_END: :REG : Input Prov (Gp 3) :abrv: IN3PROV :ADDR: 0x9c STRI :RWCI: r/w :MSB LSB NibName Description 2 AUXEN 1 = Enable Star In group 3 to use sync and ref from group 2 1 B2EN 1 = Enable hardware AIS Insert upon B2* Fail or Loss-of-Ref, 1 = normal / enable 0 CRBP Clock Recovery Bypass (reference mode for STRIN bit-5) 1 = bypass = 51.84 MHz anti-phase mode 0 = normal = 6.48 MHz reference mode :hini: 0x06 :aini: 0x00 :cmnt: Bit 2 is for OC12 drop applications where all 3 drops get sync and ref from the Group 2 Star Bus :REG_END: :REG : Input ES Alignment (Gp 3) :abrv: IN3ESALGN :ADDR: 0x9e STRI :RWCI: r :MSB LSB NibName Description 3 0 ES<3:0> ES Align Input Elastic Store alignment position :cmnt: 5-6 is centered, C-F is near spill. Star In Status register, bit<4> detects alignment fail. :REG_END: :REG : Input D1* byte, A-side (Gp 3) :abrv: IN3D1A :ADDR: 0xa0 STRI :RWCI: r :MSB LSB NibName Description 7 0 D1*<7:0> D1* input byte, A-side :aini: 0x00 :cmnt: New for SAMP :REG_END: :REG : Input D2* byte, A-side (Gp 3) :abrv: IN3D2A :ADDR: 0xa2 STRI :RWCI: r :MSB LSB NibName Description 7 0 D2*<7:0> D2* input byte, A-side :aini: 0xff :cmnt: New for SAMP :REG_END: :REG : Input D1* byte, B-side (Gp 3) :abrv: IN3D1B :ADDR: 0xa4 STRI :RWCI: r :MSB LSB NibName Description 7 0 D1*<7:0> D1* input byte, B-side :aini: 0x00 :cmnt: New for SAMP :REG_END: :REG : Input D2* byte, B-side (Gp 3) :abrv: IN3D2B :ADDR: 0xa6 STRI :RWCI: r :MSB LSB NibName Description 7 0 D2*<7:0> D2* input byte, B-side :aini: 0xff :cmnt: New for SAMP :REG_END: :REG : Input D1/D2 Change Interrupt (Gp 3) :abrv: IN3DBC :ADDR: 0xa8 STRI :RWCI: c\i :mask: 0xaa STRI :MSB LSB NibName Description 3 D1A 1 = Change in A side D1* byte 2 D2A 1 = Change in A side D2* byte 1 D1B 1 = Change in B side D1* byte 0 D2B 1 = Change in B side D2* byte :hini: :aini: :sini: :cmnt: New for SAMP :REG_END: :REG : Input D1/D2 Change Interrupt Mask (Gp 3) :abrv: IN3DBM :ADDR: 0xaa STRI :RWCI: r\w :mask: :MSB LSB NibName Description 3 D1A 1 = Mask Change in A side D1* byte 2 D2A 1 = Mask Change in A side D2* byte 1 D1B 1 = Mask Change in B side D1* byte 0 D2B 1 = Mask Change in B side D2* byte :hini: :aini: :sini: :cmnt: New for SAMP :REG_END: // STS IN DPI :REG : STS In Parity Error :abrv: In ParErr :ADDR: 0x0 STSI :RWCI: c :MSB LSB NibName Description 0 ERR 1 = Parity Error :cmnt: :REG_END: :REG : STS-VT Input Mux Ctrl :abrv: VT In Sel Ctrl :ADDR: 0x2 STSI :RWCI: r/w :MSB LSB NibName Description 1 0 SEL<1:0> 3 - Bypass VT Pointer Processor, STS Passthru 2 - Select STS Input from VT Pointer Processor Block C 1 - Select STS Input from VT Pointer Processor Block B 0 - Select STS Input from VT Pointer Processor Block A :cmnt: Reg ::0x2 STSI:: Controls STS #1 ... Reg ::0x18 STSI:: controls STS#12 :rept: 0x001 0x0c :gskp: :REG_END: :REG : Pseudo-Random Mode :abrv: In PSRMode :ADDR: 0x1a STSI :RWCI: r/w :MSB LSB NibName Description 5 OC3 1 = MXDX12 OC3 mode (mux sts 1,2,3 to 2,5,8), 0 = normal 4 GD 1 = Generate, 0 = Detect 3 2 MD<1:0> 3 = PSR Data in Payload 2 = PSR Data in SPE 1 = PSR Data in all but STAR bytes (A1,A2,K1*,K2*,E2*) 0/Gen =1 => Payload Data Bytes = Col#, MSB = 1 for Row0 0/Det_=0 => Pass Data Through 1 HEN 1 = H1,H2 = 522, 0 = Normal/Passthrough 0 AEN 1 = A1,A2 framing byte insert, 0 = Passthrough :hini: 0x00 :aini: 0x00 :cmnt: Bit 5 new for SAMP :REG_END: :REG : Pseudo-Random Upper Mode :abrv: In PSRUMode :ADDR: 0x1c STSI :RWCI: r/w :mask: :MSB LSB NibName Description 4 1 SEL<3:0> STS Select - Selects STS Input 11 to 0 for Checking 0 ALGN 1 = Aligned Mode, 0 = Stagger Mode :hini: :aini: :sini: :cmnt: :REG_END: :REG : Payload Input PSR Data Error Detect :abrv: In PSRDet :ADDR: 0x1e STSI :RWCI: c :mask: :MSB LSB NibName Description 1 A1A2 1 = A1A2 Mismatch Error Detected 0 ERR 1 = PSR Error Detected :hini: :aini: :sini: :cmnt: :REG_END: :REG : Inband Parity Error :abrv: IBPERR :ADDR: 0x20 STSI :RWCI: c\i :mask: 0x22 STSI :MSB LSB NibName Description 11 0 IBP 1 = Inband Parity Error on STS input Bit 11 - STS #12, Bit 0 - STS #1 :hini: :aini: :sini: :cmnt: New for SAMP :REG_END: :REG : Inband Parity Error Mask :abrv: IBPMSK :ADDR: 0x22 STSI :RWCI: r/w :mask: :MSB LSB NibName Description 11 0 IBP 1 = Mask Inband Parity Error on STS input Bit 11 - STS #12, Bit 0 - STS #1 :hini: :aini: :sini: :cmnt: New for SAMP :REG_END: // STS OUT DPI :REG : STS Out PSR Error :abrv: Out PSRErr :ADDR: 0x0 STSO :RWCI: c :MSB LSB NibName Description 1 A1A2 1 = A1/A2 Mismatch Error Detected 0 PSRD Err 1 = Pseudo-Random Data Error Detected :REG_END: :REG : STS-VT Output Mux Control :abrv: VT Out Sel Ctrl :ADDR: 0x2 STSO :RWCI: r/w :MSB LSB NibName Description 1 0 SEL<1:0> 3 - Bypass VT Pointer Processor, STS passthru 2 - Select STS Output from VT Pointer Processor Block C 1 - Select STS Output from VT Pointer Processor Block B 0 - Select STS Output from VT Pointer Processor Block A :cmnt: Register ::0x2 STSO:: controls STS #1 ... Register ::0x18 STSO:: controls STS #12 :rept: 0x1 0x0c :gskp: :REG_END: :REG : Pseudo-Random Mode 1 (12 x STS Insert) :abrv: Out PSRMode 1 :ADDR: 0x1a STSO :RWCI: r/w :MSB LSB NibName Description 11 IBP 1 = Enable F1* Inband Parity Insertion 10 OC3 1 = MXDX12 OC3 mode (mux sts 1,2,3 to 2,5,8), 0 = normal 9 6 SEL<3:0> Selects STS 11 to 0 for Checking 5 ALGN 1 = Aligned Data, 0 = Staggered Data 4 GD 1 = Generate, 0 = Detect 3 2 MD<1:0> 3 = PSR Data in Payload 2 = PSR Data in SPE 1 = PSR Data in all but STAR bytes (A1,A2,K1*,K2*,E2*) 0/Gen =1 => Payload Data Bytes = Col#, MSB = 1 for Row0 0/Det_=0 => Pass Data Through & Byte Monitor Active 1 HEN 1 = H1,H2 = 522, 0 = Normal/Passthrough 0 AEN 1 = A1,A2 framing byte insert, 0 = Passthrough :hini: 0x00 :aini: 0x00 :cmnt: Bit 10 & 11 new for SAMP :REG_END: :REG : Pseudo-Random Gen 2 Mode (3 X VT Insert) :abrv: Out PSRMode 2 :ADDR: 0x1c STSO :RWCI: r/w :MSB LSB NibName Description 5 ALGN 1 = Aligned Data, 0 = Staggered Data 4 GD 1 = Generate, 0 = Detect 3 2 MD<1:0> 3 = PSR Data in Payload 2 = PSR Data in SPE 1 = PSR Data in all but STAR bytes (A1,A2,K1*,K2*,E2*) 0/Gen =1 => Payload Data Bytes = Col#, MSB = 1 for Row0 0/Det_=0 => Pass Data Through & Byte Monitor Active 1 HEN 1 = H1,H2 = 522, 0 = Normal/Passthrough 0 AEN 1 = A1,A2 framing byte insert, 0 = Passthrough :REG_END: :REG : VT Multiframe Counter Offset :abrv: VTMF Cnt :ADDR: 0x1e STSO :RWCI: r/w :mask: :MSB LSB NibName Description 15 14 MF<1:0> MultiFrame Offset (0 - 3) 13 10 ROW<3:0> Frame Row Offset (0 - 8) 9 3 COL<6:0> Frame Column Offset (0 - 89) 2 0 BIT<2:0> Frame Bit Offset (0 - 7) :hini: :aini: :sini: :cmnt: :REG_END: :REG : B3 10e-3 Err Thresh :abrv: b3err10e3 :ADDR: 0x000 STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 5 0 D<5:0> Errored Block Thresh :hini: :aini: :sini: :cmnt: B3 errors are accumulated over 1 ms sampling period and block is considered errored when this threshold is exceeded :REG_END: :REG : B3 10e-3 Act Thresh :abrv: b3act10e3 :ADDR: 0x002 STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 7 4 UAT Upper Activation Threshold 3 0 LAT Lower Deactivation Threshold :hini: :aini: :sini: :cmnt: Counts errored blocks every sampling period, alarm declared when count exceeds upper thresh, and removed when below lower thresh. :REG_END: :REG : B3 10e-4 Err Thresh :abrv: b3err10e4 :ADDR: 0x004 STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 4 0 D<4:0> Errored Block Thresh :hini: :aini: :sini: :cmnt: B3 errors are accumulated over 4 ms sampling period and block is considered errored when this threshold is exceeded :REG_END: :REG : B3 10e-4 Act Thresh :abrv: b3act10e4 :ADDR: 0x006 STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 7 4 UAT Upper Activation Threshold 3 0 LAT Lower Deactivation Threshold :hini: :aini: :sini: :cmnt: Counts errored blocks every sampling period, alarm declared when count exceeds upper thresh, and removed when below lower thresh. :REG_END: :REG : B3 STS3c 10e-3 Err Thresh :abrv: b3errc10e3 :ADDR: 0x008 STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 5 0 D<5:0> Errored Block Thresh :hini: :aini: :sini: :cmnt: B3 errors are accumulated over 1 ms sampling period and block is considered errored when this threshold is exceeded :REG_END: :REG : B3 STS3c 10e-3 Act Thresh :abrv: b3actc10e3 :ADDR: 0x00a STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 7 4 UAT Upper Activation Threshold 3 0 LAT Lower Deactivation Threshold :hini: :aini: :sini: :cmnt: Counts errored blocks every sampling period, alarm declared when count exceeds upper thresh, and removed when below lower thresh. :REG_END: :REG : B3 STS3c 10e-4 Err Thresh :abrv: b3errc10e4 :ADDR: 0x00c STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 4 0 D<4:0> Errored Block Thresh :hini: :aini: :sini: :cmnt: B3 errors are accumulated over 4 ms sampling period and block is considered errored when this threshold is exceeded :REG_END: :REG : B3 STS3c 10e-4 Act Thresh :abrv: b3actc10e4 :ADDR: 0x00e STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 7 4 UAT Upper Activation Threshold 3 0 LAT Lower Deactivation Threshold :hini: :aini: :sini: :cmnt: Counts errored blocks every sampling period, alarm declared when count exceeds upper thresh, and removed when below lower thresh. :REG_END: :REG : STS3c B3 BER Enable :abrv: B3CEN :ADDR: 0x10 STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 3 STS1 STS #1, 1 = STS3c mode 2 STS4 STS #4, 1 = STS3c mode 1 STS7 STS #7, 1 = STS3c mode 0 STS10 STS #10, 1 = STS3c mode :hini: :aini: :sini: :cmnt: :REG_END: :REG : STS PM AIS Interrupt :abrv: STSAINT :ADDR: 0x012 STSPM :RWCI: c :mask: :MSB LSB NibName Description 11 STS12 1 = AIS in STS1 #12 PM Int Reg ::0x56 STSPM:: 10 STS11 1 = AIS in STS1 #11 PM Int Reg ::0x54 STSPM:: 9 STS10 1 = AIS in STS1 #10 PM Int Reg ::0x52 STSPM:: 8 STS9 1 = AIS in STS1 #9 PM Int Reg ::0x50 STSPM:: 7 STS8 1 = AIS in STS1 #8 PM Int Reg ::0x4e STSPM:: 6 STS7 1 = AIS in STS1 #7 PM Int Reg ::0x4c STSPM:: 5 STS6 1 = AIS in STS1 #6 PM Int Reg ::0x4a STSPM:: 4 STS5 1 = AIS in STS1 #5 PM Int Reg ::0x48 STSPM:: 3 STS4 1 = AIS in STS1 #4 PM Int Reg ::0x46 STSPM:: 2 STS3 1 = AIS in STS1 #3 PM Int Reg ::0x44 STSPM:: 1 STS2 1 = AIS in STS1 #2 PM Int Reg ::0x42 STSPM:: 0 STS1 1 = AIS in STS1 #1 PM Int Reg ::0x40 STSPM:: :hini: :aini: :sini: :cmnt: 1 - Unmasked AIS bit active in STS PM Interface Int Register :REG_END: :REG : STS PM Interrupt :abrv: STSINT :ADDR: 0x014 STSPM :RWCI: c :mask: :MSB LSB NibName Description 11 STS12 1 = Int in STS1 #12 PM Int Reg ::0x56 STSPM:: 10 STS11 1 = Int in STS1 #11 PM Int Reg ::0x54 STSPM:: 9 STS10 1 = Int in STS1 #10 PM Int Reg ::0x52 STSPM:: 8 STS9 1 = Int in STS1 #9 PM Int Reg ::0x50 STSPM:: 7 STS8 1 = Int in STS1 #8 PM Int Reg ::0x4e STSPM:: 6 STS7 1 = Int in STS1 #7 PM Int Reg ::0x4c STSPM:: 5 STS6 1 = Int in STS1 #6 PM Int Reg ::0x4a STSPM:: 4 STS5 1 = Int in STS1 #5 PM Int Reg ::0x48 STSPM:: 3 STS4 1 = Int in STS1 #4 PM Int Reg ::0x46 STSPM:: 2 STS3 1 = Int in STS1 #3 PM Int Reg ::0x44 STSPM:: 1 STS2 1 = Int in STS1 #2 PM Int Reg ::0x42 STSPM:: 0 STS1 1 = Int in STS1 #1 PM Int Reg ::0x40 STSPM:: :hini: :aini: :sini: :cmnt: 1 - Unmasked BPE3, BPE4, UNEQ, or C2MS bit active in STS PM Int Register :REG_END: :REG : Auto STS PathAIS Insert on BER 10e-3 :abrv: B10E3AIS :ADDR: 0x16 STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 11 0 STS<12:1> 1 = Enable auto insert of STS Path AIS to VT Pointer Processor block upon BER 10e-3 threshold detection :hini: :aini: :sini: :cmnt: :REG_END: :REG : Auto STS PathAIS Insert on BER 10e-4 :abrv: B10E4AIS :ADDR: 0x18 STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 11 0 STS<12:1> 1 = Enable auto insert of STS Path AIS to VT Pointer Processor block upon BER 10e-4 threshold detection :hini: :aini: :sini: :cmnt: :REG_END: :REG : B3 Error Count STS # :abrv: B3CNT :ADDR: 0x20 STSPM :RWCI: r :mask: :MSB LSB NibName Description 15 0 D<15:0> :hini: :aini: :sini: :rept: 0x1 0xc :cmnt: :REG_END: :REG : STS PM Status STS #r# :abrv: STSSTAT#r# :ADDR: 0x40 STSPM :RWCI: r/i :mask: 0x60 STSPM :MSB LSB NibName Description 4 BPE3 1 = BER 10e-3 Threshold Exceeded 3 BPE4 1 = BER 10e-4 Threshold Exceeded 2 PAIS 1 = STS Path AIS Detected 1 UNEQ 1 = STS Path Unequipped Detected 0 C2MS 1 = C2 Mismatch Detected :hini: :aini: :sini: :rept: 0x1 0xc :cmnt: :REG_END: :REG : STS PM Int Mask STS # :abrv: STSMSK :ADDR: 0x60 STSPM :RWCI: r/w :mask: :MSB LSB NibName Description 4 BPE3 1 = BER 10e-3 Threshold Exceeded 3 BPE4 1 = BER 10e-4 Threshold Exceeded 2 PAIS 1 = STS Path AIS Detected 1 UNEQ 1 = STS Path Unequipped Detected 0 C2MS 1 = C2 Mismatch Detected :hini: :aini: :sini: :rept: 0x1 0xc :cmnt: :REG_END: :REG : VT Ptr Proc Input Selection (3 of 12) :abrv: VTPPSEL :ADDR: 0x0 VTPP :RWCI: r/w :mask: :MSB LSB NibName Description 11 8 VTC<3:0> Selects STS input for VT Block C 7 4 VTB<3:0> Selects STS input for VT Block B 3 0 VTA<3:0> Selects STS input for VT Block A :hini: :aini: :sini: :cmnt: Select values - 0:STS1, 11:STS12, 12:all 0s, 13-15: all 1s :REG_END: :REG : VT Ptr Proc PJC Select :abrv: VTPJCSEL :ADDR: 0x2 VTPP :RWCI: r/w :mask: :MSB LSB NibName Description 6 5 VTBLK<1:0> Select VT Ptr Proc Block for PJC monitoring 00 = Block A 01 = Block B 10 = Block C 4 0 VTSEL<4:0> Select VT for PJC Monitoring, 0-27 for VT #1-28 :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Input Positive PJC :abrv: VTIPJCP :ADDR: 0x4 VTPP :RWCI: r :mask: :MSB LSB NibName Description 8 0 D :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Input Negative PJC :abrv: VTIPJCN :ADDR: 0x6 VTPP :RWCI: r :mask: :MSB LSB NibName Description 8 0 D :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Output Positive PJC :abrv: VTOPJCP :ADDR: 0x8 VTPP :RWCI: r :mask: :MSB LSB NibName Description 8 0 D :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Output Negative PJC :abrv: VTOPJCN :ADDR: 0xa VTPP :RWCI: r :mask: :MSB LSB NibName Description 8 0 D :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Ptr Proc Size Monitor Select :abrv: VTSZSEL :ADDR: 0xc VTPP :RWCI: r/w :mask: :MSB LSB NibName Description 6 5 VTBLK<1:0> Select VT Ptr Proc Block for Size monitoring 00 = Block A 01 = Block B 10 = Block C 4 0 VTSEL<4:0> Select VT for Size Monitoring, 0-27 for VT #1-28 :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Size Monitor :abrv: VTSIZE :ADDR: 0xe VTPP :RWCI: r :mask: :MSB LSB NibName Description 1 0 D<1:0> Monitors VT selected from VT Size Select Register VT Size 00 = VT6 01 = VT3 10 = VT2 11 = VT1.5 :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Multiframe Loss Interrupt :abrv: VTMFLS :ADDR: 0x10 VTPP :RWCI: c/i :mask: 0x12 VTPP :MSB LSB NibName Description 2 MFC 1 = H4 Multiframe Loss, VT Block C 1 MFB 1 = H4 Multiframe Loss, VT Block B 0 MFA 1 = H4 Multiframe Loss, VT Block A :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Multiframe Loss Interrupt Mask :abrv: VTMFMSK :ADDR: 0x12 VTPP :RWCI: r/w :mask: :MSB LSB NibName Description 2 MFC 1 = Mask H4 MF Loss Int, VT Block C 1 MFB 1 = Mask H4 MF Loss Int, VT Block B 0 MFA 1 = Mask H4 MF Loss Int, VT Block A :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Pointer Processor Prov Block A :abrv: VTPROVA :ADDR: 0x14 VTPP :RWCI: r/w :mask: :MSB LSB NibName Description 9 LAIS 1 = Enable Line Side VT AIS/LOP to NE VT AIS insertion 8 7 V4<1:0> V4* Robbed Overhead Enable, Valid for all 3 VT Blocks 11 = V5 byte in V4* 10 = VT Switch Crit. in V4* 01 = P1 Compatible Robbed V4* 00 = V4* disabled, V4 Passthru 6 DAIS 1 = Auto AIS insert disabled 5 MAIS 1 = Auto AIS on MF Fail enabled 4 VTAIS 1 = Force Insert VT AIS into all VTs of STS1 3 - No Function, was VT Elastic Store Filter Threshold 2 - No Function 1 0 SZ<1:0> VT Size provisioning 00 = VT6 01 = VT3 10 = VT2 11 = VT1.5 :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Pointer Processor Prov Block B :abrv: VTPROVB :ADDR: 0x016 VTPP :MSB LSB NibName Description 6 DAIS 1 = Auto AIS insert disabled 5 MAIS 1 = Auto AIS on MF Fail enabled 4 VTAIS 1 = Force Insert VT AIS into all VTs of STS1 3 - No Function, was VT Elastic Store Filter Threshold 2 - No Function 1 0 SZ<1:0> VT Size provisiion 00 = VT6 01 = VT3 10 = VT2 11 = VT1.5 :cmnt: Bits 6:0 same as register ::0x14 VTPP:: :REG_END: :REG : VT Pointer Processor Prov Block C :abrv: VTPROVC :ADDR: 0x018 VTPP :MSB LSB NibName Description 6 DAIS 1 = Auto AIS insert disabled 5 MAIS 1 = Auto AIS on MF Fail enabled 4 VTAIS 1 = Force Insert VT AIS into all VTs of STS1 3 - No Function, was VT Elastic Store Filter Threshold 2 - No Function 1 0 SZ<1:0> VT Size provisiion 00 = VT6 01 = VT3 10 = VT2 11 = VT1.5 :cmnt: Bits 6:0 same as register ::0x14 VTPP:: :REG_END: :REG : VT Blk A Alm VT #r# :abrv: VTAINT#r# :ADDR: 0x0 VTINT :RWCI: r/i :mask: 0x0 VTMSK :MSB LSB NibName Description 7 5 LBL<2:0> VT Signal Label (Unfiltered) 4 LOP 1 = VT LOP is detected for 8 frames 3 BPE3 1 = BIP2 BER 10e-3 threshold exceeded 2 BPE4 1 = BIP2 BER 10e-3 threshold exceeded 1 AIS 1 = VT AIS is detected for 3 frames 0 UNEQ 1 = VT Unequipped code detected for 5 frames :hini: :aini: :sini: :rept: 0x1 0x1c :gskp: :cmnt: :REG_END: :REG : VT Blk B Alm VT #r# :abrv: VTBINT#r# :ADDR: 0x40 VTINT :mask: 0x40 VTMSK :same: 0x00 VTINT :rept: 0x1 0x1c :REG_END: :REG : VT Blk C Alm VT #r# :abrv: VTCINT#r# :ADDR: 0x80 VTINT :mask: 0x80 VTMSK :same: 0x00 VTINT :rept: 0x1 0x1c :gskp: :REG_END: :REG : VT Blk A Mask VT # :abrv: VTAMSK :ADDR: 0x0 VTMSK :RWCI: r :mask: :MSB LSB NibName Description 4 LOP 1 = Mask VT LOP Int 3 BPE3 1 = Mask BIP2 BER 10e-3 Int 2 BPE4 1 = Mask BIP2 BER 10e-3 Int 1 AIS 1 = Mask VT AIS Int 0 UNEQ 1 = Mask VT Unequipped Int :hini: :aini: :sini: :rept: 0x1 0x1c :gskp: :cmnt: :REG_END: :REG : VT Blk B Mask VT # :abrv: VTBMSK :ADDR: 0x40 VTMSK :same: 0x00 VTMSK :rept: 0x1 0x1c :gskp: :REG_END: :REG : VT Blk C Mask VT # :abrv: VTCMSK :ADDR: 0x80 VTMSK :same: 0x00 VTMSK :rept: 0x1 0x1c :gskp: :REG_END: :REG : VT BIP2 Accumulation Count Block A VT # :abrv: VTBIPA :ADDR: 0x0 VTPM2 :RWCI: r :mask: :MSB LSB NibName Description 11 0 D<11:0> BIP2 Error Accumulation :hini: :aini: :sini: :rept: 0x1 0x1c :gskp: :cmnt: :REG_END: :REG : VT BIP2 Accumulation Count Block B VT # :abrv: VTBIPB :ADDR: 0x40 VTPM2 :RWCI: r :mask: :MSB LSB NibName Description 11 0 D<11:0> BIP2 Error Accumulation :hini: :aini: :sini: :rept: 0x1 0x1c :gskp: :cmnt: :REG_END: :REG : VT BIP2 Accumulation Count Block C VT # :abrv: VTBIPC :ADDR: 0x80 VTPM2 :RWCI: r :mask: :MSB LSB NibName Description 11 0 D<11:0> BIP2 Error Accumulation :hini: :aini: :sini: :rept: 0x1 0x1c :gskp: :cmnt: :REG_END: :REG : VT 1.5 10e-3 Error Threshold :abrv: VT15ERR3 :ADDR: 0x0 VTTHSH :RWCI: r/w :mask: :MSB LSB NibName Description 3 0 D<3:0> Errored Block Thresh, BIP2 errors are accumulated over sampling period and block is considered errored when this threshold is exceeded :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT 1.5 10e-3 Error Window :abrv: VT15WIN3 :ADDR: 0x2 VTTHSH :RWCI: r/w :mask: :MSB LSB NibName Description 3 0 D<3:0> Errored Block Sampling period. 500 uS (VT Multiframe) increments 0 = 1 MF, 500 uS...F = 16 MF, 8 mS :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT 1.5 10e-3 Activation Threshold :abrv: VT15ACT3 :ADDR: 0x4 VTTHSH :RWCI: r/w :mask: :MSB LSB NibName Description 7 4 UAT<3:0> Upper Activation Threshold 3 0 LAT<3:0> Lower Deactivation Threshold :hini: :aini: :sini: :cmnt: Counts errored blocks every sampling period. Alarm declared when count exceeds upper thresh, and removed when below lower thresh :REG_END: :REG : VT 1.5 10e-4 Error Threshold :abrv: VT15ERR4 :ADDR: 0x6 VTTHSH :RWCI: r/w :mask: :MSB LSB NibName Description 3 0 D<3:0> Errored Block Thresh, BIP2 errors are accumulated over sampling period and block is considered errored when this threshold is exceeded :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT 1.5 10e-4 Error Window :abrv: VT15WIN4 :ADDR: 0x8 VTTHSH :RWCI: r/w :mask: :MSB LSB NibName Description 3 0 D<3:0> Errored Block Sampling period. 500 uS (VT Multiframe) increments 0 = 1 MF, 500 uS...F = 16 MF, 8 mS :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT 1.5 10e-4 Activation Threshold :abrv: VT15ACT4 :ADDR: 0xa VTTHSH :RWCI: r/w :mask: :MSB LSB NibName Description 7 4 UAT<3:0> Upper Activation Threshold 3 0 LAT<3:0> Lower Deactivation Threshold :hini: :aini: :sini: :cmnt: Counts errored blocks every sampling period. Alarm declared when count exceeds upper thresh, and removed when below lower thresh :REG_END: :REG : VT 2 10e-3 Error Threshold :abrv: VT2ERR3 :ADDR: 0x10 VTTHSH :same: 0x0 VTTHSH :REG_END: :REG : VT 2 10e-3 Error Window :abrv: VT2WIN3 :ADDR: 0x12 VTTHSH :same: 0x2 VTTHSH :REG_END: :REG : VT 2 10e-3 Activation Threshold :abrv: VT2ACT3 :ADDR: 0x14 VTTHSH :same: 0x4 VTTHSH :REG_END: :REG : VT 2 10e-4 Error Threshold :abrv: VT2ERR4 :ADDR: 016 VTTHSH :same: 0x6 VTTHSH :REG_END: :REG : VT 2 10e-4 Error Window :abrv: VT2WIN4 :ADDR: 0x18 VTTHSH :same: 0x8 VTTHSH :REG_END: :REG : VT 2 10e-4 Activation Threshold :abrv: VT2ACT4 :ADDR: 0x1a VTTHSH :same: 0xa VTTHSH :REG_END: :REG : VT 3 10e-3 Error Threshold :abrv: VT3ERR3 :ADDR: 0x20 VTTHSH :same: 0x0 VTTHSH :REG_END: :REG : VT 3 10e-3 Error Window :abrv: VT3WIN3 :ADDR: 0x22 VTTHSH :same: 0x2 VTTHSH :REG_END: :REG : VT 3 10e-3 Activation Threshold :abrv: VT3ACT3 :ADDR: 0x24 VTTHSH :same: 0x4 VTTHSH :REG_END: :REG : VT 3 10e-4 Error Threshold :abrv: VT3ERR4 :ADDR: 026 VTTHSH :same: 0x6 VTTHSH :REG_END: :REG : VT 3 10e-4 Error Window :abrv: VT3WIN4 :ADDR: 0x28 VTTHSH :same: 0x8 VTTHSH :REG_END: :REG : VT 3 10e-4 Activation Threshold :abrv: VT3ACT4 :ADDR: 0x2a VTTHSH :same: 0xa VTTHSH :REG_END: :REG : VT 6 10e-3 Error Threshold :abrv: VT6ERR3 :ADDR: 0x30 VTTHSH :same: 0x0 VTTHSH :REG_END: :REG : VT 6 10e-3 Error Window :abrv: VT6WIN3 :ADDR: 0x32 VTTHSH :same: 0x2 VTTHSH :REG_END: :REG : VT 6 10e-3 Activation Threshold :abrv: VT6ACT3 :ADDR: 0x34 VTTHSH :same: 0x4 VTTHSH :REG_END: :REG : VT 6 10e-4 Error Threshold :abrv: VT6ERR4 :ADDR: 036 VTTHSH :same: 0x6 VTTHSH :REG_END: :REG : VT 6 10e-4 Error Window :abrv: VT6WIN4 :ADDR: 0x38 VTTHSH :same: 0x8 VTTHSH :REG_END: :REG : VT 6 10e-4 Activation Threshold :abrv: VT6ACT4 :ADDR: 0x3a VTTHSH :same: 0xa VTTHSH :REG_END: :REG : VT Block A Interrupt Summary #1 :abrv: VTASUM1 :ADDR: 0x0 VTSUM :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = Unmasked BER or UNEQ int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 28 - summary of BER or UNEQ for reg ::0x036 VTINT::, VT 15 - summary of reg ::0x01c VTINT:: :REG_END: :REG : VT Block A Interrupt Summary #2 :abrv: VTASUM2 :ADDR: 0x2 VTSUM :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = Unmasked BER or UNEQ int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 14 - summary of BER or UNEQ for reg ::0x01a VTINT::, VT 1 - summary of reg ::0x0 VTINT:: :REG_END: :REG : VT Block B Interrupt Summary #1 :abrv: VTBSUM1 :ADDR: 0x4 VTSUM :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = Unmasked BER or UNEQ int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 28 - summary of BER or UNEQ for reg ::0x076 VTINT::, VT 15 - summary of reg ::0x05c VTINT:: :REG_END: :REG : VT Block B Interrupt Summary #2 :abrv: VTBSUM2 :ADDR: 0x6 VTSUM :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = Unmasked BER or UNEQ int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 14 - summary of BER or UNEQ for reg ::0x05a VTINT::, VT 1 - summary of reg ::0x40 VTINT:: :REG_END: :REG : VT Block C Interrupt Summary #1 :abrv: VTCSUM1 :ADDR: 0x8 VTSUM :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = Unmasked BER or UNEQ int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 28 - summary of BER or UNEQ for reg ::0x0b6 VTINT::, VT 15 - summary of reg ::0x09c VTINT:: :REG_END: :REG : VT Block C Interrupt Summary #2 :abrv: VTCSUM2 :ADDR: 0xa VTSUM :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = Unmasked BER or UNEQ int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 14 - summary of BER or UNEQ for reg ::0x09a VTINT::, VT 1 - summary of reg ::0x80 VTINT:: :REG_END: :REG : VT Block A1 RDI Status (one bit RDI) :abrv: VTARDI1 :ADDR: 0x0 VTRDI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = VT RDI (1 bit) detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block A2 RDI Status (one bit RDI) :abrv: VTARDI2 :ADDR: 0x2 VTRDI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = VT RDI (1 bit) detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block B1 RDI Status (one bit RDI) :abrv: VTBRDI1 :ADDR: 0x4 VTRDI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = VT RDI (1 bit) detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block B2 RDI Status (one bit RDI) :abrv: VTBRDI2 :ADDR: 0x6 VTRDI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = VT RDI (1 bit) detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block C1 RDI Status (one bit RDI) :abrv: VTCRDI1 :ADDR: 0x8 VTRDI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = VT RDI (1 bit) detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block C2 RDI Status (one bit RDI) :abrv: VTCRDI2 :ADDR: 0xa VTRDI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = VT RDI (1 bit) detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block A1 RFI Status :abrv: VTARFI1 :ADDR: 0x0 VTRFI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = VT RFI detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block A2 RFI Status :abrv: VTARFI2 :ADDR: 0x2 VTRFI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = VT RFI detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block B1 RFI Status :abrv: VTBRFI1 :ADDR: 0x4 VTRFI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = VT RFI detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block B2 RFI Status :abrv: VTBRFI2 :ADDR: 0x6 VTRFI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = VT RFI detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block C1 RFI Status :abrv: VTCRFI1 :ADDR: 0x8 VTRFI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = VT RFI detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block C2 RFI Status :abrv: VTCRFI2 :ADDR: 0xa VTRFI :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = VT RFI detected for 10 frames :hini: :aini: :sini: :cmnt: :REG_END: :REG : VT Block A AIS Interrupt Summary #1 :abrv: VTAAIS1 :ADDR: 0x0 VTAIS :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = Unmasked AIS or LOP int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 28 - summary of AIS or LOP for reg ::0x036 VTINT::, VT 15 - summary of reg ::0x01c VTINT:: :REG_END: :REG : VT Block A AIS Interrupt Summary #2 :abrv: VTAAIS2 :ADDR: 0x2 VTAIS :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = Unmasked AIS or LOP int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 14 - summary of AIS or LOP for reg ::0x01a VTINT::, VT 1 - summary of reg ::0x0 VTINT:: :REG_END: :REG : VT Block B AIS Interrupt Summary #1 :abrv: VTBAIS1 :ADDR: 0x4 VTAIS :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = Unmasked AIS or LOP int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 28 - summary of AIS or LOP for reg ::0x076 VTINT::, VT 15 - summary of reg ::0x05c VTINT:: :REG_END: :REG : VT Block B AIS Interrupt Summary #2 :abrv: VTBAIS2 :ADDR: 0x6 VTAIS :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = Unmasked AIS or LOP int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 14 - summary of AIS or LOP for reg ::0x05a VTINT::, VT 1 - summary of reg ::0x40 VTINT:: :REG_END: :REG : VT Block C AIS Interrupt Summary #1 :abrv: VTCAIS1 :ADDR: 0x8 VTAIS :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<28:15> 1 = Unmasked AIS or LOP int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 28 - summary of AIS or LOP for reg ::0x0b6 VTINT::, VT 15 - summary of reg ::0x09c VTINT:: :REG_END: :REG : VT Block C AIS Interrupt Summary #2 :abrv: VTCAIS2 :ADDR: 0xa VTAIS :RWCI: c :mask: :MSB LSB NibName Description 13 0 VT<14:1> 1 = Unmasked AIS or LOP int active in corresponding VT Int Reg :hini: :aini: :sini: :cmnt: VT 14 - summary of AIS or LOP for reg ::0x09a VTINT::, VT 1 - summary of reg ::0x80 VTINT:: :REG_END: