/* PARSE: 1ASICSTUB begin */ /***************************************************************************/ /***************************************************************************/ #define SAMP_C #include /* for strlen, strcpy */ #include #include "global.h" #include "pba_def.h" #include "cpu_regs.h" #include "cmd_util.h" #include "sbi_rel1.h" #include "pba_cmds.h" #include "packet.h" #include "romm_equ.h" #include "commands.h" #include "vtpa.h" #include "vtpa_int_msgs.c" typedef char byte; #define PROV 0 #define STAT 1 #define TRUE 1 #define FALSE 0 /* Register struct */ struct asic_reg_struct { offset_type offset; /* offset from asic_base */ byte prov_or_stat; /* read/write access indicator */ data_type mask; /* bit mask for valid bits */ data_type reg_default; /* default value for reg */ byte group; /* group/block reg belongs to */ }; typedef void (*ASIC_INTR_PTR)(ubyte, ubyte); /* Interrupt structure */ struct intr_struct { offset_type offset; /* offset from asic_base */ data_type rptctrl_value; /* value of report_ctrl */ data_type mask_option_value; /* to mask or not mask each bit */ offset_type masked_by_offset; /* which asic register masks it */ ASIC_INTR_PTR intr_function; /* fcn to be called when interrupt occurs */ }; struct asic_reg_config_list { offset_type offset; data_type value; }; #define BKGND_TIMEOUT (6000) /* microseconds between backgnd task */ static ulong bkgnd_time; /* Background task holdoff */ /* asic access macros, set up for 16 bits only right now, can change */ /* all accesses to the asic should uses these. Automatic */ /* masking on reads */ #define WRITE_ASIC(base, offset, data) (*((data_type*)(base + (offset_type)(offset))) = data) #define READ_ASIC(base, offset, mask) (data_type)(*((data_type*)(base + (offset_type)(offset))) & mask) static unsigned int find_index(unsigned int offset); extern uword inslot_debouncer; #define ASIC_INTR 1 #define INTR_CLR 0 struct asic_reg_config_list vtpa_cfg_a[] = { 0x0000, 0x007f, /* init 0x0000 to 0x007f, etc */ NULL, NULL }; struct asic_reg_config_list vtpa_cfg_b[] = { 0x0000, 0x003f, /* init 0x0000 to 0x003f, etc */ 0x0002, 0x000f, NULL, NULL }; struct asic_config_num { byte relative_to_defaults; /* if relative to defaults, then you default first, then set values */ struct asic_reg_config_list *reg_configs; }; struct asic_config_num vtpa_configs[] = { 0x01, vtpa_cfg_a, 0x00, vtpa_cfg_b }; struct asic_reg_struct vtpa[NUM_SAMP_REGS] = { /* offset, STAT/PROV, mask, dflt, group_number */ 0x0000, STAT, 0x000f, 0x0000, SAMP_GLOB1_REGS , /*0x00000000 Clock Sel Interrupt*/ 0x0002, PROV, 0x000f, 0x0000, SAMP_GLOB1_REGS , /*0x00000002 Clock Select Int Mask*/ 0x0004, STAT, 0x0007, 0x0000, SAMP_GLOB1_REGS , /*0x00000004 STAR I/F Interrupt Summary*/ 0x0006, PROV, 0x0007, 0x0000, SAMP_GLOB1_REGS , /*0x00000006 STAR I/F Summary Mask*/ 0x0008, STAT, 0x01ff, 0x0000, SAMP_GLOB1_REGS , /*0x00000008 Master Interrupt Summary*/ 0x000a, PROV, 0x01ff, 0x0000, SAMP_GLOB1_REGS , /*0x0000000a Master Interrupt Mask*/ 0x000c, PROV, 0x00ff, 0x0000, SAMP_GLOB1_REGS , /*0x0000000c UCFAIL & POR*/ 0x000e, STAT, 0x0001, 0x0000, SAMP_GLOB1_REGS , /*0x0000000e Clock Select Status*/ 0x0010, PROV, 0x0007, 0x0000, SAMP_GLOB1_REGS , /*0x00000010 Global Provisioning*/ 0x0012, PROV, 0xffff, 0x0000, SAMP_GLOB1_REGS , /*0x00000012 Test Provisioning*/ 0x0014, PROV, 0x003f, 0x0000, SAMP_GLOB1_REGS , /*0x00000014 Clock Select Provisioning*/ 0x0016, PROV, 0xffff, 0x0000, SAMP_GLOB1_REGS , /*0x00000016 Diagnostic Register*/ 0x0018, STAT, 0xffff, 0x0000, SAMP_GLOB1_REGS , /*0x00000018 Device Type & ID*/ 0x001a, PROV, 0x00ff, 0x0000, SAMP_GLOB1_REGS , /*0x0000001a Generic I/O Control*/ 0x001c, STAT, 0x00ff, 0x0000, SAMP_GLOB1_REGS , /*0x0000001c Extraneous Pin State Reflections*/ 0x001e, STAT, 0x00ff, 0x0000, SAMP_GLOB1_REGS , /*0x0000001e Generic Input Change*/ 0x0020, PROV, 0x00ff, 0x0000, SAMP_GLOB1_REGS , /*0x00000020 Generic Input Mask*/ 0x0022, STAT, 0x00ff, 0x0000, SAMP_GLOB1_REGS , /*0x00000022 Generic Input Status*/ 0x0040, PROV, 0x007f, 0x000e, SAMP_STRO1_REGS , /*0x00000040 Star Out Mode2 (Gp # 1)*/ 0x0042, PROV, 0x00ff, 0x000f, SAMP_STRO1_REGS , /*0x00000042 Star Out Mode1 (Gp # 1)*/ 0x0044, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x00000044 Output E2* Byte (Gp # 1)*/ 0x0046, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x00000046 Output K2* Byte (Gp # 1)*/ 0x0048, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x00000048 Output K1* Byte (Gp # 1)*/ 0x004a, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x0000004a Output D2* Byte (Gp # 1)*/ 0x004c, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x0000004c Output D1* Byte (Gp # 1)*/ 0x0080, PROV, 0x007f, 0x000e, SAMP_STRO1_REGS , /*0x00000080 Star Out Mode2 (Gp # 2)*/ 0x0082, PROV, 0x00ff, 0x000f, SAMP_STRO1_REGS , /*0x00000082 Star Out Mode1 (Gp # 2)*/ 0x0084, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x00000084 Star Out E2* Byte (Gp # 2)*/ 0x0086, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x00000086 Star Out K2* Byte (Gp # 2)*/ 0x0088, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x00000088 Star Out K1* Byte (Gp # 2)*/ 0x008a, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x0000008a Output D2* Byte (Gp # 2)*/ 0x008c, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x0000008c Output D1* Byte (Gp # 2)*/ 0x00c0, PROV, 0x007f, 0x000e, SAMP_STRO1_REGS , /*0x000000c0 Star Out Mode2 (Gp # 3)*/ 0x00c2, PROV, 0x00ff, 0x000f, SAMP_STRO1_REGS , /*0x000000c2 Star Out Mode1 (Gp # 3)*/ 0x00c4, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x000000c4 Star Out E2* Byte (Gp # 3)*/ 0x00c6, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x000000c6 Star Out K2* Byte (Gp # 3)*/ 0x00c8, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x000000c8 Star Out K1* Byte (Gp # 3)*/ 0x00ca, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x000000ca Output D2* Byte (Gp # 3)*/ 0x00cc, PROV, 0x00ff, 0x0000, SAMP_STRO1_REGS , /*0x000000cc Output D1* Byte (Gp # 3)*/ 0x0100, STAT, 0x000f, 0x0000, SAMP_TMG1_REGS , /*0x00000100 Timing Window Status*/ 0x0102, STAT, 0x001f, 0x0000, SAMP_TMG1_REGS , /*0x00000102 Timing Interrupt Reg*/ 0x0104, PROV, 0x001f, 0x0000, SAMP_TMG1_REGS , /*0x00000104 Timing Int Mask Reg*/ 0x0106, PROV, 0x001f, 0x0000, SAMP_TMG1_REGS , /*0x00000106 Timing Provisioning*/ 0x0108, PROV, 0x1fff, 0x0000, SAMP_TMG1_REGS , /*0x00000108 Timing Offset S1 Lower*/ 0x010a, PROV, 0x0003, 0x0000, SAMP_TMG1_REGS , /*0x0000010a Timing Offset S1 Upper*/ 0x010c, PROV, 0x1fff, 0x0000, SAMP_TMG1_REGS , /*0x0000010c Timing Offset S2 Lower*/ 0x010e, PROV, 0x0003, 0x0000, SAMP_TMG1_REGS , /*0x0000010e Timing Offset S2 Upper*/ 0x0110, PROV, 0x1fff, 0x0000, SAMP_TMG1_REGS , /*0x00000110 Timing Offset S3 Lower*/ 0x0112, PROV, 0x0003, 0x0000, SAMP_TMG1_REGS , /*0x00000112 Timing Offset S3 Upper*/ 0x0114, PROV, 0x03ff, 0x0002, SAMP_TMG1_REGS , /*0x00000114 Parallel Offset S4*/ 0x0140, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x00000140 Input K1* byte, A-side (Gp 1)*/ 0x0142, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x00000142 Input K2* byte, A-side (Gp 1)*/ 0x0144, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x00000144 Input E2* byte, A-side (Gp 1)*/ 0x0146, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x00000146 Input K1* byte, B-side (Gp 1)*/ 0x0148, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x00000148 Input K2* byte, B-side (Gp 1)*/ 0x014a, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x0000014a Input E2* byte, B-side (Gp 1)*/ 0x014c, STAT, 0x001f, 0x0000, SAMP_STRI1_REGS , /*0x0000014c Star In Status (Gp 1)*/ 0x014e, STAT, 0x0003, 0x0001, SAMP_STRI1_REGS , /*0x0000014e Star In A side Int1 (Gp 1)*/ 0x0150, STAT, 0x0003, 0x0001, SAMP_STRI1_REGS , /*0x00000150 Star In B side Int1 (Gp 1)*/ 0x0152, STAT, 0x0007, 0x0003, SAMP_STRI1_REGS , /*0x00000152 Star In A side Int2 (Gp 1)*/ 0x0154, STAT, 0x0007, 0x0003, SAMP_STRI1_REGS , /*0x00000154 Star In B side Int2 (Gp 1)*/ 0x0156, PROV, 0x001f, 0x0000, SAMP_STRI1_REGS , /*0x00000156 Star In Int Mask (Gp 1)*/ 0x0158, STAT, 0x001f, 0x0000, SAMP_STRI1_REGS , /*0x00000158 Star In Int Summary (Gp 1)*/ 0x015a, PROV, 0x000f, 0x0007, SAMP_STRI1_REGS , /*0x0000015a Input Star Mode (Gp 1)*/ 0x015c, PROV, 0x0007, 0x0000, SAMP_STRI1_REGS , /*0x0000015c Input Prov (Gp 1)*/ 0x015e, STAT, 0x000f, 0x0000, SAMP_STRI1_REGS , /*0x0000015e Input ES Alignment (Gp 1)*/ 0x0160, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x00000160 Input D1* byte, A-side (Gp 1)*/ 0x0162, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x00000162 Input D2* byte, A-side (Gp 1)*/ 0x0164, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x00000164 Input D1* byte, B-side (Gp 1)*/ 0x0166, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x00000166 Input D2* byte, B-side (Gp 1)*/ 0x0168, STAT, 0x000f, 0x0000, SAMP_STRI1_REGS , /*0x00000168 Input D1/D2 Change Interrupt (Gp 1)*/ 0x016a, PROV, 0x000f, 0x0000, SAMP_STRI1_REGS , /*0x0000016a Input D1/D2 Change Interrupt Mask (Gp 1)*/ 0x0180, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x00000180 Input K1* byte, A-side (Gp 2)*/ 0x0182, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x00000182 Input K2* byte, A-side (Gp 2)*/ 0x0184, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x00000184 Input E2* byte, A-side (Gp 2)*/ 0x0186, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x00000186 Input K1* byte, B-side (Gp 2)*/ 0x0188, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x00000188 Input K2* byte, B-side (Gp 2)*/ 0x018a, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x0000018a Input E2* byte, B-side (Gp 2)*/ 0x018c, STAT, 0x001f, 0x0000, SAMP_STRI1_REGS , /*0x0000018c Star In Status (Gp 2)*/ 0x018e, STAT, 0x0003, 0x0001, SAMP_STRI1_REGS , /*0x0000018e Star In A side Int1 (Gp 2)*/ 0x0190, STAT, 0x0003, 0x0001, SAMP_STRI1_REGS , /*0x00000190 Star In B side Int1 (Gp 2)*/ 0x0192, STAT, 0x0007, 0x0003, SAMP_STRI1_REGS , /*0x00000192 Star In A side Int2 (Gp 2)*/ 0x0194, STAT, 0x0007, 0x0003, SAMP_STRI1_REGS , /*0x00000194 Star In B side Int2 (Gp 2)*/ 0x0196, PROV, 0x001f, 0x0000, SAMP_STRI1_REGS , /*0x00000196 Star In Int Mask (Gp 2)*/ 0x0198, STAT, 0x001f, 0x0000, SAMP_STRI1_REGS , /*0x00000198 Star In Int Summary (Gp 2)*/ 0x019a, PROV, 0x000f, 0x0007, SAMP_STRI1_REGS , /*0x0000019a Input Star Mode (Gp 2)*/ 0x019c, PROV, 0x0007, 0x0000, SAMP_STRI1_REGS , /*0x0000019c Input Prov (Gp 2)*/ 0x019e, STAT, 0x000f, 0x0000, SAMP_STRI1_REGS , /*0x0000019e Input ES Alignment (Gp 2)*/ 0x01a0, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x000001a0 Input D1* byte, A-side (Gp 2)*/ 0x01a2, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x000001a2 Input D2* byte, A-side (Gp 2)*/ 0x01a4, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x000001a4 Input D1* byte, B-side (Gp 2)*/ 0x01a6, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x000001a6 Input D2* byte, B-side (Gp 2)*/ 0x01a8, STAT, 0x000f, 0x0000, SAMP_STRI1_REGS , /*0x000001a8 Input D1/D2 Change Interrupt (Gp 2)*/ 0x01aa, PROV, 0x000f, 0x0000, SAMP_STRI1_REGS , /*0x000001aa Input D1/D2 Change Interrupt Mask (Gp 2)*/ 0x01c0, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x000001c0 Input K1* byte, A-side (Gp 3)*/ 0x01c2, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x000001c2 Input K2* byte, A-side (Gp 3)*/ 0x01c4, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x000001c4 Input E2* byte, A-side (Gp 3)*/ 0x01c6, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x000001c6 Input K1* byte, B-side (Gp 3)*/ 0x01c8, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x000001c8 Input K2* byte, B-side (Gp 3)*/ 0x01ca, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x000001ca Input E2* byte, B-side (Gp 3)*/ 0x01cc, STAT, 0x001f, 0x0000, SAMP_STRI1_REGS , /*0x000001cc Star In Status (Gp 3)*/ 0x01ce, STAT, 0x0003, 0x0001, SAMP_STRI1_REGS , /*0x000001ce Star In A side Int1 (Gp 3)*/ 0x01d0, STAT, 0x0003, 0x0001, SAMP_STRI1_REGS , /*0x000001d0 Star In B side Int1 (Gp 3)*/ 0x01d2, STAT, 0x0007, 0x0003, SAMP_STRI1_REGS , /*0x000001d2 Star In A side Int2 (Gp 3)*/ 0x01d4, STAT, 0x0007, 0x0003, SAMP_STRI1_REGS , /*0x000001d4 Star In B side Int2 (Gp 3)*/ 0x01d6, PROV, 0x001f, 0x0000, SAMP_STRI1_REGS , /*0x000001d6 Star In Int Mask (Gp 3)*/ 0x01d8, STAT, 0x001f, 0x0000, SAMP_STRI1_REGS , /*0x000001d8 Star In Int Summary (Gp 3)*/ 0x01da, PROV, 0x000f, 0x0007, SAMP_STRI1_REGS , /*0x000001da Input Star Mode (Gp 3)*/ 0x01dc, PROV, 0x0007, 0x0000, SAMP_STRI1_REGS , /*0x000001dc Input Prov (Gp 3)*/ 0x01de, STAT, 0x000f, 0x0000, SAMP_STRI1_REGS , /*0x000001de Input ES Alignment (Gp 3)*/ 0x01e0, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x000001e0 Input D1* byte, A-side (Gp 3)*/ 0x01e2, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x000001e2 Input D2* byte, A-side (Gp 3)*/ 0x01e4, STAT, 0x00ff, 0x0000, SAMP_STRI1_REGS , /*0x000001e4 Input D1* byte, B-side (Gp 3)*/ 0x01e6, STAT, 0x00ff, 0x00ff, SAMP_STRI1_REGS , /*0x000001e6 Input D2* byte, B-side (Gp 3)*/ 0x01e8, STAT, 0x000f, 0x0000, SAMP_STRI1_REGS , /*0x000001e8 Input D1/D2 Change Interrupt (Gp 3)*/ 0x01ea, PROV, 0x000f, 0x0000, SAMP_STRI1_REGS , /*0x000001ea Input D1/D2 Change Interrupt Mask (Gp 3)*/ 0x0200, STAT, 0x0001, 0x0000, SAMP_STSI1_REGS , /*0x00000200 STS In Parity Error*/ 0x0202, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x00000202 STS-VT Input Mux Ctrl#1*/ 0x0204, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x00000204 STS-VT Input Mux Ctrl#2*/ 0x0206, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x00000206 STS-VT Input Mux Ctrl#3*/ 0x0208, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x00000208 STS-VT Input Mux Ctrl#4*/ 0x020a, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x0000020a STS-VT Input Mux Ctrl#5*/ 0x020c, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x0000020c STS-VT Input Mux Ctrl#6*/ 0x020e, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x0000020e STS-VT Input Mux Ctrl#7*/ 0x0210, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x00000210 STS-VT Input Mux Ctrl#8*/ 0x0212, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x00000212 STS-VT Input Mux Ctrl#9*/ 0x0214, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x00000214 STS-VT Input Mux Ctrl#10*/ 0x0216, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x00000216 STS-VT Input Mux Ctrl#11*/ 0x0218, PROV, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x00000218 STS-VT Input Mux Ctrl#12*/ 0x021a, PROV, 0x003f, 0x0000, SAMP_STSI1_REGS , /*0x0000021a Pseudo-Random Mode*/ 0x021c, PROV, 0x001f, 0x0000, SAMP_STSI1_REGS , /*0x0000021c Pseudo-Random Upper Mode*/ 0x021e, STAT, 0x0003, 0x0000, SAMP_STSI1_REGS , /*0x0000021e Payload Input PSR Data Error Detect*/ 0x0220, STAT, 0x0fff, 0x0000, SAMP_STSI1_REGS , /*0x00000220 Inband Parity Error*/ 0x0222, PROV, 0x0fff, 0x0000, SAMP_STSI1_REGS , /*0x00000222 Inband Parity Error Mask*/ 0x0240, STAT, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x00000240 STS Out PSR Error*/ 0x0242, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x00000242 STS-VT Output Mux Control#1*/ 0x0244, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x00000244 STS-VT Output Mux Control#2*/ 0x0246, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x00000246 STS-VT Output Mux Control#3*/ 0x0248, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x00000248 STS-VT Output Mux Control#4*/ 0x024a, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x0000024a STS-VT Output Mux Control#5*/ 0x024c, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x0000024c STS-VT Output Mux Control#6*/ 0x024e, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x0000024e STS-VT Output Mux Control#7*/ 0x0250, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x00000250 STS-VT Output Mux Control#8*/ 0x0252, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x00000252 STS-VT Output Mux Control#9*/ 0x0254, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x00000254 STS-VT Output Mux Control#10*/ 0x0256, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x00000256 STS-VT Output Mux Control#11*/ 0x0258, PROV, 0x0003, 0x0000, SAMP_STSO1_REGS , /*0x00000258 STS-VT Output Mux Control#12*/ 0x025a, PROV, 0x0fff, 0x0000, SAMP_STSO1_REGS , /*0x0000025a Pseudo-Random Mode 1 (12 x STS Insert)*/ 0x025c, PROV, 0x003f, 0x0000, SAMP_STSO1_REGS , /*0x0000025c Pseudo-Random Gen 2 Mode (3 X VT Insert)*/ 0x025e, PROV, 0xffff, 0x0000, SAMP_STSO1_REGS , /*0x0000025e VT Multiframe Counter Offset*/ 0x0280, PROV, 0x003f, 0x0000, SAMP_STSPM1_REGS , /*0x00000280 B3 10e-3 Err Thresh*/ 0x0282, PROV, 0x00ff, 0x0000, SAMP_STSPM1_REGS , /*0x00000282 B3 10e-3 Act Thresh*/ 0x0284, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x00000284 B3 10e-4 Err Thresh*/ 0x0286, PROV, 0x00ff, 0x0000, SAMP_STSPM1_REGS , /*0x00000286 B3 10e-4 Act Thresh*/ 0x0288, PROV, 0x003f, 0x0000, SAMP_STSPM1_REGS , /*0x00000288 B3 STS3c 10e-3 Err Thresh*/ 0x028a, PROV, 0x00ff, 0x0000, SAMP_STSPM1_REGS , /*0x0000028a B3 STS3c 10e-3 Act Thresh*/ 0x028c, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x0000028c B3 STS3c 10e-4 Err Thresh*/ 0x028e, PROV, 0x00ff, 0x0000, SAMP_STSPM1_REGS , /*0x0000028e B3 STS3c 10e-4 Act Thresh*/ 0x0290, PROV, 0x000f, 0x0000, SAMP_STSPM1_REGS , /*0x00000290 STS3c B3 BER Enable*/ 0x0292, STAT, 0x0fff, 0x0000, SAMP_STSPM1_REGS , /*0x00000292 STS PM AIS Interrupt*/ 0x0294, STAT, 0x0fff, 0x0000, SAMP_STSPM1_REGS , /*0x00000294 STS PM Interrupt*/ 0x0296, PROV, 0x0fff, 0x0000, SAMP_STSPM1_REGS , /*0x00000296 Auto STS PathAIS Insert on BER 10e-3*/ 0x0298, PROV, 0x0fff, 0x0000, SAMP_STSPM1_REGS , /*0x00000298 Auto STS PathAIS Insert on BER 10e-4*/ 0x02a0, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002a0 B3 Error Count STS ##1*/ 0x02a2, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002a2 B3 Error Count STS ##2*/ 0x02a4, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002a4 B3 Error Count STS ##3*/ 0x02a6, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002a6 B3 Error Count STS ##4*/ 0x02a8, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002a8 B3 Error Count STS ##5*/ 0x02aa, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002aa B3 Error Count STS ##6*/ 0x02ac, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002ac B3 Error Count STS ##7*/ 0x02ae, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002ae B3 Error Count STS ##8*/ 0x02b0, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002b0 B3 Error Count STS ##9*/ 0x02b2, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002b2 B3 Error Count STS ##10*/ 0x02b4, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002b4 B3 Error Count STS ##11*/ 0x02b6, STAT, 0xffff, 0x0000, SAMP_STSPM1_REGS , /*0x000002b6 B3 Error Count STS ##12*/ 0x02c0, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002c0 STS PM Status STS #1*/ 0x02c2, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002c2 STS PM Status STS #2*/ 0x02c4, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002c4 STS PM Status STS #3*/ 0x02c6, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002c6 STS PM Status STS #4*/ 0x02c8, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002c8 STS PM Status STS #5*/ 0x02ca, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002ca STS PM Status STS #6*/ 0x02cc, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002cc STS PM Status STS #7*/ 0x02ce, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002ce STS PM Status STS #8*/ 0x02d0, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002d0 STS PM Status STS #9*/ 0x02d2, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002d2 STS PM Status STS #10*/ 0x02d4, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002d4 STS PM Status STS #11*/ 0x02d6, STAT, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002d6 STS PM Status STS #12*/ 0x02e0, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002e0 STS PM Int Mask STS ##1*/ 0x02e2, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002e2 STS PM Int Mask STS ##2*/ 0x02e4, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002e4 STS PM Int Mask STS ##3*/ 0x02e6, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002e6 STS PM Int Mask STS ##4*/ 0x02e8, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002e8 STS PM Int Mask STS ##5*/ 0x02ea, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002ea STS PM Int Mask STS ##6*/ 0x02ec, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002ec STS PM Int Mask STS ##7*/ 0x02ee, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002ee STS PM Int Mask STS ##8*/ 0x02f0, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002f0 STS PM Int Mask STS ##9*/ 0x02f2, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002f2 STS PM Int Mask STS ##10*/ 0x02f4, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002f4 STS PM Int Mask STS ##11*/ 0x02f6, PROV, 0x001f, 0x0000, SAMP_STSPM1_REGS , /*0x000002f6 STS PM Int Mask STS ##12*/ 0x0300, PROV, 0x0fff, 0x0000, SAMP_VTPP1_REGS , /*0x00000300 VT Ptr Proc Input Selection (3 of 12)*/ 0x0302, PROV, 0x007f, 0x0000, SAMP_VTPP1_REGS , /*0x00000302 VT Ptr Proc PJC Select*/ 0x0304, STAT, 0x01ff, 0x0000, SAMP_VTPP1_REGS , /*0x00000304 VT Input Positive PJC*/ 0x0306, STAT, 0x01ff, 0x0000, SAMP_VTPP1_REGS , /*0x00000306 VT Input Negative PJC*/ 0x0308, STAT, 0x01ff, 0x0000, SAMP_VTPP1_REGS , /*0x00000308 VT Output Positive PJC*/ 0x030a, STAT, 0x01ff, 0x0000, SAMP_VTPP1_REGS , /*0x0000030a VT Output Negative PJC*/ 0x030c, PROV, 0x007f, 0x0000, SAMP_VTPP1_REGS , /*0x0000030c VT Ptr Proc Size Monitor Select*/ 0x030e, STAT, 0x0003, 0x0000, SAMP_VTPP1_REGS , /*0x0000030e VT Size Monitor*/ 0x0310, STAT, 0x0007, 0x0000, SAMP_VTPP1_REGS , /*0x00000310 VT Multiframe Loss Interrupt*/ 0x0312, PROV, 0x0007, 0x0000, SAMP_VTPP1_REGS , /*0x00000312 VT Multiframe Loss Interrupt Mask*/ 0x0314, PROV, 0x03ff, 0x0000, SAMP_VTPP1_REGS , /*0x00000314 VT Pointer Processor Prov Block A*/ 0x0316, STAT, 0x007f, 0x0000, SAMP_VTPP1_REGS , /*0x00000316 VT Pointer Processor Prov Block B*/ 0x0318, STAT, 0x007f, 0x0000, SAMP_VTPP1_REGS , /*0x00000318 VT Pointer Processor Prov Block C*/ 0x0400, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000400 VT Blk A Alm VT #1*/ 0x0402, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000402 VT Blk A Alm VT #2*/ 0x0404, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000404 VT Blk A Alm VT #3*/ 0x0406, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000406 VT Blk A Alm VT #4*/ 0x0408, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000408 VT Blk A Alm VT #5*/ 0x040a, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000040a VT Blk A Alm VT #6*/ 0x040c, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000040c VT Blk A Alm VT #7*/ 0x040e, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000040e VT Blk A Alm VT #8*/ 0x0410, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000410 VT Blk A Alm VT #9*/ 0x0412, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000412 VT Blk A Alm VT #10*/ 0x0414, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000414 VT Blk A Alm VT #11*/ 0x0416, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000416 VT Blk A Alm VT #12*/ 0x0418, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000418 VT Blk A Alm VT #13*/ 0x041a, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000041a VT Blk A Alm VT #14*/ 0x041c, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000041c VT Blk A Alm VT #15*/ 0x041e, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000041e VT Blk A Alm VT #16*/ 0x0420, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000420 VT Blk A Alm VT #17*/ 0x0422, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000422 VT Blk A Alm VT #18*/ 0x0424, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000424 VT Blk A Alm VT #19*/ 0x0426, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000426 VT Blk A Alm VT #20*/ 0x0428, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000428 VT Blk A Alm VT #21*/ 0x042a, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000042a VT Blk A Alm VT #22*/ 0x042c, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000042c VT Blk A Alm VT #23*/ 0x042e, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000042e VT Blk A Alm VT #24*/ 0x0430, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000430 VT Blk A Alm VT #25*/ 0x0432, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000432 VT Blk A Alm VT #26*/ 0x0434, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000434 VT Blk A Alm VT #27*/ 0x0436, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000436 VT Blk A Alm VT #28*/ 0x0440, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000440 VT Blk B Alm VT #1*/ 0x0442, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000442 VT Blk B Alm VT #2*/ 0x0444, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000444 VT Blk B Alm VT #3*/ 0x0446, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000446 VT Blk B Alm VT #4*/ 0x0448, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000448 VT Blk B Alm VT #5*/ 0x044a, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000044a VT Blk B Alm VT #6*/ 0x044c, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000044c VT Blk B Alm VT #7*/ 0x044e, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000044e VT Blk B Alm VT #8*/ 0x0450, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000450 VT Blk B Alm VT #9*/ 0x0452, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000452 VT Blk B Alm VT #10*/ 0x0454, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000454 VT Blk B Alm VT #11*/ 0x0456, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000456 VT Blk B Alm VT #12*/ 0x0458, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000458 VT Blk B Alm VT #13*/ 0x045a, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000045a VT Blk B Alm VT #14*/ 0x045c, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000045c VT Blk B Alm VT #15*/ 0x045e, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000045e VT Blk B Alm VT #16*/ 0x0460, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000460 VT Blk B Alm VT #17*/ 0x0462, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000462 VT Blk B Alm VT #18*/ 0x0464, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000464 VT Blk B Alm VT #19*/ 0x0466, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000466 VT Blk B Alm VT #20*/ 0x0468, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000468 VT Blk B Alm VT #21*/ 0x046a, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000046a VT Blk B Alm VT #22*/ 0x046c, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000046c VT Blk B Alm VT #23*/ 0x046e, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000046e VT Blk B Alm VT #24*/ 0x0470, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000470 VT Blk B Alm VT #25*/ 0x0472, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000472 VT Blk B Alm VT #26*/ 0x0474, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000474 VT Blk B Alm VT #27*/ 0x0476, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000476 VT Blk B Alm VT #28*/ 0x0480, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000480 VT Blk C Alm VT #1*/ 0x0482, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000482 VT Blk C Alm VT #2*/ 0x0484, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000484 VT Blk C Alm VT #3*/ 0x0486, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000486 VT Blk C Alm VT #4*/ 0x0488, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000488 VT Blk C Alm VT #5*/ 0x048a, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000048a VT Blk C Alm VT #6*/ 0x048c, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000048c VT Blk C Alm VT #7*/ 0x048e, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000048e VT Blk C Alm VT #8*/ 0x0490, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000490 VT Blk C Alm VT #9*/ 0x0492, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000492 VT Blk C Alm VT #10*/ 0x0494, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000494 VT Blk C Alm VT #11*/ 0x0496, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000496 VT Blk C Alm VT #12*/ 0x0498, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x00000498 VT Blk C Alm VT #13*/ 0x049a, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000049a VT Blk C Alm VT #14*/ 0x049c, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000049c VT Blk C Alm VT #15*/ 0x049e, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x0000049e VT Blk C Alm VT #16*/ 0x04a0, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004a0 VT Blk C Alm VT #17*/ 0x04a2, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004a2 VT Blk C Alm VT #18*/ 0x04a4, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004a4 VT Blk C Alm VT #19*/ 0x04a6, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004a6 VT Blk C Alm VT #20*/ 0x04a8, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004a8 VT Blk C Alm VT #21*/ 0x04aa, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004aa VT Blk C Alm VT #22*/ 0x04ac, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004ac VT Blk C Alm VT #23*/ 0x04ae, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004ae VT Blk C Alm VT #24*/ 0x04b0, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004b0 VT Blk C Alm VT #25*/ 0x04b2, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004b2 VT Blk C Alm VT #26*/ 0x04b4, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004b4 VT Blk C Alm VT #27*/ 0x04b6, STAT, 0x00ff, 0x0000, SAMP_VTINT1_REGS , /*0x000004b6 VT Blk C Alm VT #28*/ 0x0700, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000700 VT Blk A Mask VT ##1*/ 0x0702, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000702 VT Blk A Mask VT ##2*/ 0x0704, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000704 VT Blk A Mask VT ##3*/ 0x0706, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000706 VT Blk A Mask VT ##4*/ 0x0708, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000708 VT Blk A Mask VT ##5*/ 0x070a, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000070a VT Blk A Mask VT ##6*/ 0x070c, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000070c VT Blk A Mask VT ##7*/ 0x070e, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000070e VT Blk A Mask VT ##8*/ 0x0710, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000710 VT Blk A Mask VT ##9*/ 0x0712, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000712 VT Blk A Mask VT ##10*/ 0x0714, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000714 VT Blk A Mask VT ##11*/ 0x0716, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000716 VT Blk A Mask VT ##12*/ 0x0718, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000718 VT Blk A Mask VT ##13*/ 0x071a, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000071a VT Blk A Mask VT ##14*/ 0x071c, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000071c VT Blk A Mask VT ##15*/ 0x071e, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000071e VT Blk A Mask VT ##16*/ 0x0720, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000720 VT Blk A Mask VT ##17*/ 0x0722, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000722 VT Blk A Mask VT ##18*/ 0x0724, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000724 VT Blk A Mask VT ##19*/ 0x0726, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000726 VT Blk A Mask VT ##20*/ 0x0728, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000728 VT Blk A Mask VT ##21*/ 0x072a, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000072a VT Blk A Mask VT ##22*/ 0x072c, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000072c VT Blk A Mask VT ##23*/ 0x072e, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000072e VT Blk A Mask VT ##24*/ 0x0730, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000730 VT Blk A Mask VT ##25*/ 0x0732, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000732 VT Blk A Mask VT ##26*/ 0x0734, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000734 VT Blk A Mask VT ##27*/ 0x0736, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000736 VT Blk A Mask VT ##28*/ 0x0740, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000740 VT Blk B Mask VT ##1*/ 0x0742, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000742 VT Blk B Mask VT ##2*/ 0x0744, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000744 VT Blk B Mask VT ##3*/ 0x0746, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000746 VT Blk B Mask VT ##4*/ 0x0748, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000748 VT Blk B Mask VT ##5*/ 0x074a, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000074a VT Blk B Mask VT ##6*/ 0x074c, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000074c VT Blk B Mask VT ##7*/ 0x074e, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000074e VT Blk B Mask VT ##8*/ 0x0750, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000750 VT Blk B Mask VT ##9*/ 0x0752, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000752 VT Blk B Mask VT ##10*/ 0x0754, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000754 VT Blk B Mask VT ##11*/ 0x0756, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000756 VT Blk B Mask VT ##12*/ 0x0758, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000758 VT Blk B Mask VT ##13*/ 0x075a, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000075a VT Blk B Mask VT ##14*/ 0x075c, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000075c VT Blk B Mask VT ##15*/ 0x075e, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000075e VT Blk B Mask VT ##16*/ 0x0760, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000760 VT Blk B Mask VT ##17*/ 0x0762, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000762 VT Blk B Mask VT ##18*/ 0x0764, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000764 VT Blk B Mask VT ##19*/ 0x0766, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000766 VT Blk B Mask VT ##20*/ 0x0768, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000768 VT Blk B Mask VT ##21*/ 0x076a, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000076a VT Blk B Mask VT ##22*/ 0x076c, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000076c VT Blk B Mask VT ##23*/ 0x076e, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000076e VT Blk B Mask VT ##24*/ 0x0770, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000770 VT Blk B Mask VT ##25*/ 0x0772, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000772 VT Blk B Mask VT ##26*/ 0x0774, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000774 VT Blk B Mask VT ##27*/ 0x0776, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000776 VT Blk B Mask VT ##28*/ 0x0780, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000780 VT Blk C Mask VT ##1*/ 0x0782, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000782 VT Blk C Mask VT ##2*/ 0x0784, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000784 VT Blk C Mask VT ##3*/ 0x0786, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000786 VT Blk C Mask VT ##4*/ 0x0788, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000788 VT Blk C Mask VT ##5*/ 0x078a, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000078a VT Blk C Mask VT ##6*/ 0x078c, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000078c VT Blk C Mask VT ##7*/ 0x078e, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000078e VT Blk C Mask VT ##8*/ 0x0790, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000790 VT Blk C Mask VT ##9*/ 0x0792, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000792 VT Blk C Mask VT ##10*/ 0x0794, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000794 VT Blk C Mask VT ##11*/ 0x0796, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000796 VT Blk C Mask VT ##12*/ 0x0798, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x00000798 VT Blk C Mask VT ##13*/ 0x079a, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000079a VT Blk C Mask VT ##14*/ 0x079c, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000079c VT Blk C Mask VT ##15*/ 0x079e, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x0000079e VT Blk C Mask VT ##16*/ 0x07a0, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007a0 VT Blk C Mask VT ##17*/ 0x07a2, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007a2 VT Blk C Mask VT ##18*/ 0x07a4, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007a4 VT Blk C Mask VT ##19*/ 0x07a6, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007a6 VT Blk C Mask VT ##20*/ 0x07a8, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007a8 VT Blk C Mask VT ##21*/ 0x07aa, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007aa VT Blk C Mask VT ##22*/ 0x07ac, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007ac VT Blk C Mask VT ##23*/ 0x07ae, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007ae VT Blk C Mask VT ##24*/ 0x07b0, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007b0 VT Blk C Mask VT ##25*/ 0x07b2, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007b2 VT Blk C Mask VT ##26*/ 0x07b4, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007b4 VT Blk C Mask VT ##27*/ 0x07b6, STAT, 0x001f, 0x0000, SAMP_VTMSK1_REGS , /*0x000007b6 VT Blk C Mask VT ##28*/ 0x0a00, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a00 VT BIP2 Accumulation Count Block A VT ##1*/ 0x0a02, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a02 VT BIP2 Accumulation Count Block A VT ##2*/ 0x0a04, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a04 VT BIP2 Accumulation Count Block A VT ##3*/ 0x0a06, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a06 VT BIP2 Accumulation Count Block A VT ##4*/ 0x0a08, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a08 VT BIP2 Accumulation Count Block A VT ##5*/ 0x0a0a, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a0a VT BIP2 Accumulation Count Block A VT ##6*/ 0x0a0c, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a0c VT BIP2 Accumulation Count Block A VT ##7*/ 0x0a0e, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a0e VT BIP2 Accumulation Count Block A VT ##8*/ 0x0a10, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a10 VT BIP2 Accumulation Count Block A VT ##9*/ 0x0a12, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a12 VT BIP2 Accumulation Count Block A VT ##10*/ 0x0a14, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a14 VT BIP2 Accumulation Count Block A VT ##11*/ 0x0a16, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a16 VT BIP2 Accumulation Count Block A VT ##12*/ 0x0a18, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a18 VT BIP2 Accumulation Count Block A VT ##13*/ 0x0a1a, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a1a VT BIP2 Accumulation Count Block A VT ##14*/ 0x0a1c, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a1c VT BIP2 Accumulation Count Block A VT ##15*/ 0x0a1e, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a1e VT BIP2 Accumulation Count Block A VT ##16*/ 0x0a20, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a20 VT BIP2 Accumulation Count Block A VT ##17*/ 0x0a22, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a22 VT BIP2 Accumulation Count Block A VT ##18*/ 0x0a24, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a24 VT BIP2 Accumulation Count Block A VT ##19*/ 0x0a26, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a26 VT BIP2 Accumulation Count Block A VT ##20*/ 0x0a28, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a28 VT BIP2 Accumulation Count Block A VT ##21*/ 0x0a2a, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a2a VT BIP2 Accumulation Count Block A VT ##22*/ 0x0a2c, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a2c VT BIP2 Accumulation Count Block A VT ##23*/ 0x0a2e, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a2e VT BIP2 Accumulation Count Block A VT ##24*/ 0x0a30, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a30 VT BIP2 Accumulation Count Block A VT ##25*/ 0x0a32, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a32 VT BIP2 Accumulation Count Block A VT ##26*/ 0x0a34, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a34 VT BIP2 Accumulation Count Block A VT ##27*/ 0x0a36, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a36 VT BIP2 Accumulation Count Block A VT ##28*/ 0x0a40, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a40 VT BIP2 Accumulation Count Block B VT ##1*/ 0x0a42, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a42 VT BIP2 Accumulation Count Block B VT ##2*/ 0x0a44, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a44 VT BIP2 Accumulation Count Block B VT ##3*/ 0x0a46, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a46 VT BIP2 Accumulation Count Block B VT ##4*/ 0x0a48, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a48 VT BIP2 Accumulation Count Block B VT ##5*/ 0x0a4a, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a4a VT BIP2 Accumulation Count Block B VT ##6*/ 0x0a4c, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a4c VT BIP2 Accumulation Count Block B VT ##7*/ 0x0a4e, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a4e VT BIP2 Accumulation Count Block B VT ##8*/ 0x0a50, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a50 VT BIP2 Accumulation Count Block B VT ##9*/ 0x0a52, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a52 VT BIP2 Accumulation Count Block B VT ##10*/ 0x0a54, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a54 VT BIP2 Accumulation Count Block B VT ##11*/ 0x0a56, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a56 VT BIP2 Accumulation Count Block B VT ##12*/ 0x0a58, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a58 VT BIP2 Accumulation Count Block B VT ##13*/ 0x0a5a, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a5a VT BIP2 Accumulation Count Block B VT ##14*/ 0x0a5c, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a5c VT BIP2 Accumulation Count Block B VT ##15*/ 0x0a5e, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a5e VT BIP2 Accumulation Count Block B VT ##16*/ 0x0a60, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a60 VT BIP2 Accumulation Count Block B VT ##17*/ 0x0a62, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a62 VT BIP2 Accumulation Count Block B VT ##18*/ 0x0a64, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a64 VT BIP2 Accumulation Count Block B VT ##19*/ 0x0a66, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a66 VT BIP2 Accumulation Count Block B VT ##20*/ 0x0a68, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a68 VT BIP2 Accumulation Count Block B VT ##21*/ 0x0a6a, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a6a VT BIP2 Accumulation Count Block B VT ##22*/ 0x0a6c, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a6c VT BIP2 Accumulation Count Block B VT ##23*/ 0x0a6e, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a6e VT BIP2 Accumulation Count Block B VT ##24*/ 0x0a70, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a70 VT BIP2 Accumulation Count Block B VT ##25*/ 0x0a72, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a72 VT BIP2 Accumulation Count Block B VT ##26*/ 0x0a74, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a74 VT BIP2 Accumulation Count Block B VT ##27*/ 0x0a76, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a76 VT BIP2 Accumulation Count Block B VT ##28*/ 0x0a80, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a80 VT BIP2 Accumulation Count Block C VT ##1*/ 0x0a82, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a82 VT BIP2 Accumulation Count Block C VT ##2*/ 0x0a84, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a84 VT BIP2 Accumulation Count Block C VT ##3*/ 0x0a86, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a86 VT BIP2 Accumulation Count Block C VT ##4*/ 0x0a88, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a88 VT BIP2 Accumulation Count Block C VT ##5*/ 0x0a8a, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a8a VT BIP2 Accumulation Count Block C VT ##6*/ 0x0a8c, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a8c VT BIP2 Accumulation Count Block C VT ##7*/ 0x0a8e, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a8e VT BIP2 Accumulation Count Block C VT ##8*/ 0x0a90, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a90 VT BIP2 Accumulation Count Block C VT ##9*/ 0x0a92, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a92 VT BIP2 Accumulation Count Block C VT ##10*/ 0x0a94, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a94 VT BIP2 Accumulation Count Block C VT ##11*/ 0x0a96, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a96 VT BIP2 Accumulation Count Block C VT ##12*/ 0x0a98, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a98 VT BIP2 Accumulation Count Block C VT ##13*/ 0x0a9a, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a9a VT BIP2 Accumulation Count Block C VT ##14*/ 0x0a9c, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a9c VT BIP2 Accumulation Count Block C VT ##15*/ 0x0a9e, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000a9e VT BIP2 Accumulation Count Block C VT ##16*/ 0x0aa0, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000aa0 VT BIP2 Accumulation Count Block C VT ##17*/ 0x0aa2, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000aa2 VT BIP2 Accumulation Count Block C VT ##18*/ 0x0aa4, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000aa4 VT BIP2 Accumulation Count Block C VT ##19*/ 0x0aa6, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000aa6 VT BIP2 Accumulation Count Block C VT ##20*/ 0x0aa8, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000aa8 VT BIP2 Accumulation Count Block C VT ##21*/ 0x0aaa, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000aaa VT BIP2 Accumulation Count Block C VT ##22*/ 0x0aac, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000aac VT BIP2 Accumulation Count Block C VT ##23*/ 0x0aae, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000aae VT BIP2 Accumulation Count Block C VT ##24*/ 0x0ab0, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000ab0 VT BIP2 Accumulation Count Block C VT ##25*/ 0x0ab2, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000ab2 VT BIP2 Accumulation Count Block C VT ##26*/ 0x0ab4, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000ab4 VT BIP2 Accumulation Count Block C VT ##27*/ 0x0ab6, STAT, 0x0fff, 0x0000, SAMP_VTPM21_REGS , /*0x00000ab6 VT BIP2 Accumulation Count Block C VT ##28*/ 0x0d00, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d00 VT 1.5 10e-3 Error Threshold*/ 0x0d02, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d02 VT 1.5 10e-3 Error Window*/ 0x0d04, PROV, 0x00ff, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d04 VT 1.5 10e-3 Activation Threshold*/ 0x0d06, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d06 VT 1.5 10e-4 Error Threshold*/ 0x0d08, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d08 VT 1.5 10e-4 Error Window*/ 0x0d0a, PROV, 0x00ff, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d0a VT 1.5 10e-4 Activation Threshold*/ 0x0d10, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d10 VT 2 10e-3 Error Threshold*/ 0x0d12, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d12 VT 2 10e-3 Error Window*/ 0x0d14, PROV, 0x00ff, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d14 VT 2 10e-3 Activation Threshold*/ 0x0d16, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d16 VT 2 10e-4 Error Threshold*/ 0x0d18, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d18 VT 2 10e-4 Error Window*/ 0x0d1a, PROV, 0x00ff, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d1a VT 2 10e-4 Activation Threshold*/ 0x0d20, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d20 VT 3 10e-3 Error Threshold*/ 0x0d22, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d22 VT 3 10e-3 Error Window*/ 0x0d24, PROV, 0x00ff, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d24 VT 3 10e-3 Activation Threshold*/ 0x0d26, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d26 VT 3 10e-4 Error Threshold*/ 0x0d28, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d28 VT 3 10e-4 Error Window*/ 0x0d2a, PROV, 0x00ff, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d2a VT 3 10e-4 Activation Threshold*/ 0x0d30, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d30 VT 6 10e-3 Error Threshold*/ 0x0d32, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d32 VT 6 10e-3 Error Window*/ 0x0d34, PROV, 0x00ff, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d34 VT 6 10e-3 Activation Threshold*/ 0x0d36, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d36 VT 6 10e-4 Error Threshold*/ 0x0d38, PROV, 0x000f, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d38 VT 6 10e-4 Error Window*/ 0x0d3a, PROV, 0x00ff, 0x0000, SAMP_VTTHSH1_REGS , /*0x00000d3a VT 6 10e-4 Activation Threshold*/ 0x0d40, STAT, 0x3fff, 0x0000, SAMP_VTSUM1_REGS , /*0x00000d40 VT Block A Interrupt Summary #1*/ 0x0d42, STAT, 0x3fff, 0x0000, SAMP_VTSUM1_REGS , /*0x00000d42 VT Block A Interrupt Summary #2*/ 0x0d44, STAT, 0x3fff, 0x0000, SAMP_VTSUM1_REGS , /*0x00000d44 VT Block B Interrupt Summary #1*/ 0x0d46, STAT, 0x3fff, 0x0000, SAMP_VTSUM1_REGS , /*0x00000d46 VT Block B Interrupt Summary #2*/ 0x0d48, STAT, 0x3fff, 0x0000, SAMP_VTSUM1_REGS , /*0x00000d48 VT Block C Interrupt Summary #1*/ 0x0d4a, STAT, 0x3fff, 0x0000, SAMP_VTSUM1_REGS , /*0x00000d4a VT Block C Interrupt Summary #2*/ 0x0da0, STAT, 0x3fff, 0x0000, SAMP_VTRDI1_REGS , /*0x00000da0 VT Block A1 RDI Status (one bit RDI)*/ 0x0da2, STAT, 0x3fff, 0x0000, SAMP_VTRDI1_REGS , /*0x00000da2 VT Block A2 RDI Status (one bit RDI)*/ 0x0da4, STAT, 0x3fff, 0x0000, SAMP_VTRDI1_REGS , /*0x00000da4 VT Block B1 RDI Status (one bit RDI)*/ 0x0da6, STAT, 0x3fff, 0x0000, SAMP_VTRDI1_REGS , /*0x00000da6 VT Block B2 RDI Status (one bit RDI)*/ 0x0da8, STAT, 0x3fff, 0x0000, SAMP_VTRDI1_REGS , /*0x00000da8 VT Block C1 RDI Status (one bit RDI)*/ 0x0daa, STAT, 0x3fff, 0x0000, SAMP_VTRDI1_REGS , /*0x00000daa VT Block C2 RDI Status (one bit RDI)*/ 0x0dd0, STAT, 0x3fff, 0x0000, SAMP_VTRFI1_REGS , /*0x00000dd0 VT Block A1 RFI Status*/ 0x0dd2, STAT, 0x3fff, 0x0000, SAMP_VTRFI1_REGS , /*0x00000dd2 VT Block A2 RFI Status*/ 0x0dd4, STAT, 0x3fff, 0x0000, SAMP_VTRFI1_REGS , /*0x00000dd4 VT Block B1 RFI Status*/ 0x0dd6, STAT, 0x3fff, 0x0000, SAMP_VTRFI1_REGS , /*0x00000dd6 VT Block B2 RFI Status*/ 0x0dd8, STAT, 0x3fff, 0x0000, SAMP_VTRFI1_REGS , /*0x00000dd8 VT Block C1 RFI Status*/ 0x0dda, STAT, 0x3fff, 0x0000, SAMP_VTRFI1_REGS , /*0x00000dda VT Block C2 RFI Status*/ 0x0e00, STAT, 0x3fff, 0x0000, SAMP_VTAIS1_REGS , /*0x00000e00 VT Block A AIS Interrupt Summary #1*/ 0x0e02, STAT, 0x3fff, 0x0000, SAMP_VTAIS1_REGS , /*0x00000e02 VT Block A AIS Interrupt Summary #2*/ 0x0e04, STAT, 0x3fff, 0x0000, SAMP_VTAIS1_REGS , /*0x00000e04 VT Block B AIS Interrupt Summary #1*/ 0x0e06, STAT, 0x3fff, 0x0000, SAMP_VTAIS1_REGS , /*0x00000e06 VT Block B AIS Interrupt Summary #2*/ 0x0e08, STAT, 0x3fff, 0x0000, SAMP_VTAIS1_REGS , /*0x00000e08 VT Block C AIS Interrupt Summary #1*/ 0x0e0a, STAT, 0x3fff, 0x0000, SAMP_VTAIS1_REGS , /*0x00000e0a VT Block C AIS Interrupt Summary #2*/ 0x0000, PROV, 0x000f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000000 Clock Sel Interrupt Report control*/ 0x0000, PROV, 0x000f, 0x000f, SAMP_INTCTRL11_REGS , /*0x00000000 Clock Sel Interrupt Masking Option*/ 0x0001, PROV, 0x0007, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000001 STAR I/F Interrupt Summary Report control*/ 0x0001, PROV, 0x0007, 0x0007, SAMP_INTCTRL11_REGS , /*0x00000001 STAR I/F Interrupt Summary Masking Option*/ 0x0002, PROV, 0x01ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000002 Master Interrupt Summary Report control*/ 0x0002, PROV, 0x01ff, 0x01ff, SAMP_INTCTRL11_REGS , /*0x00000002 Master Interrupt Summary Masking Option*/ 0x0003, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000003 Generic Input Change Report control*/ 0x0003, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000003 Generic Input Change Masking Option*/ 0x0004, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000004 Timing Interrupt Reg Report control*/ 0x0004, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000004 Timing Interrupt Reg Masking Option*/ 0x0005, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000005 Star In Int Summary (Gp 1) Report control*/ 0x0005, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000005 Star In Int Summary (Gp 1) Masking Option*/ 0x0006, PROV, 0x000f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000006 Input D1/D2 Change Interrupt (Gp 1) Report control*/ 0x0006, PROV, 0x000f, 0x000f, SAMP_INTCTRL11_REGS , /*0x00000006 Input D1/D2 Change Interrupt (Gp 1) Masking Option*/ 0x0007, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000007 Star In Int Summary (Gp 2) Report control*/ 0x0007, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000007 Star In Int Summary (Gp 2) Masking Option*/ 0x0008, PROV, 0x000f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000008 Input D1/D2 Change Interrupt (Gp 2) Report control*/ 0x0008, PROV, 0x000f, 0x000f, SAMP_INTCTRL11_REGS , /*0x00000008 Input D1/D2 Change Interrupt (Gp 2) Masking Option*/ 0x0009, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000009 Star In Int Summary (Gp 3) Report control*/ 0x0009, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000009 Star In Int Summary (Gp 3) Masking Option*/ 0x000a, PROV, 0x000f, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000000a Input D1/D2 Change Interrupt (Gp 3) Report control*/ 0x000a, PROV, 0x000f, 0x000f, SAMP_INTCTRL11_REGS , /*0x0000000a Input D1/D2 Change Interrupt (Gp 3) Masking Option*/ 0x000b, PROV, 0x0fff, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000000b Inband Parity Error Report control*/ 0x000b, PROV, 0x0fff, 0x0fff, SAMP_INTCTRL11_REGS , /*0x0000000b Inband Parity Error Masking Option*/ 0x000c, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000000c STS PM Status STS #1 Report control*/ 0x000c, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x0000000c STS PM Status STS #1 Masking Option*/ 0x000d, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000000d STS PM Status STS #2 Report control*/ 0x000d, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x0000000d STS PM Status STS #2 Masking Option*/ 0x000e, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000000e STS PM Status STS #3 Report control*/ 0x000e, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x0000000e STS PM Status STS #3 Masking Option*/ 0x000f, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000000f STS PM Status STS #4 Report control*/ 0x000f, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x0000000f STS PM Status STS #4 Masking Option*/ 0x0010, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000010 STS PM Status STS #5 Report control*/ 0x0010, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000010 STS PM Status STS #5 Masking Option*/ 0x0011, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000011 STS PM Status STS #6 Report control*/ 0x0011, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000011 STS PM Status STS #6 Masking Option*/ 0x0012, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000012 STS PM Status STS #7 Report control*/ 0x0012, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000012 STS PM Status STS #7 Masking Option*/ 0x0013, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000013 STS PM Status STS #8 Report control*/ 0x0013, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000013 STS PM Status STS #8 Masking Option*/ 0x0014, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000014 STS PM Status STS #9 Report control*/ 0x0014, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000014 STS PM Status STS #9 Masking Option*/ 0x0015, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000015 STS PM Status STS #10 Report control*/ 0x0015, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000015 STS PM Status STS #10 Masking Option*/ 0x0016, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000016 STS PM Status STS #11 Report control*/ 0x0016, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000016 STS PM Status STS #11 Masking Option*/ 0x0017, PROV, 0x001f, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000017 STS PM Status STS #12 Report control*/ 0x0017, PROV, 0x001f, 0x001f, SAMP_INTCTRL11_REGS , /*0x00000017 STS PM Status STS #12 Masking Option*/ 0x0018, PROV, 0x0007, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000018 VT Multiframe Loss Interrupt Report control*/ 0x0018, PROV, 0x0007, 0x0007, SAMP_INTCTRL11_REGS , /*0x00000018 VT Multiframe Loss Interrupt Masking Option*/ 0x0019, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000019 VT Blk A Alm VT #1 Report control*/ 0x0019, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000019 VT Blk A Alm VT #1 Masking Option*/ 0x001a, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000001a VT Blk A Alm VT #2 Report control*/ 0x001a, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x0000001a VT Blk A Alm VT #2 Masking Option*/ 0x001b, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000001b VT Blk A Alm VT #3 Report control*/ 0x001b, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x0000001b VT Blk A Alm VT #3 Masking Option*/ 0x001c, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000001c VT Blk A Alm VT #4 Report control*/ 0x001c, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x0000001c VT Blk A Alm VT #4 Masking Option*/ 0x001d, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000001d VT Blk A Alm VT #5 Report control*/ 0x001d, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x0000001d VT Blk A Alm VT #5 Masking Option*/ 0x001e, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000001e VT Blk A Alm VT #6 Report control*/ 0x001e, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x0000001e VT Blk A Alm VT #6 Masking Option*/ 0x001f, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000001f VT Blk A Alm VT #7 Report control*/ 0x001f, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x0000001f VT Blk A Alm VT #7 Masking Option*/ 0x0020, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000020 VT Blk A Alm VT #8 Report control*/ 0x0020, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000020 VT Blk A Alm VT #8 Masking Option*/ 0x0021, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000021 VT Blk A Alm VT #9 Report control*/ 0x0021, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000021 VT Blk A Alm VT #9 Masking Option*/ 0x0022, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000022 VT Blk A Alm VT #10 Report control*/ 0x0022, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000022 VT Blk A Alm VT #10 Masking Option*/ 0x0023, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000023 VT Blk A Alm VT #11 Report control*/ 0x0023, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000023 VT Blk A Alm VT #11 Masking Option*/ 0x0024, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000024 VT Blk A Alm VT #12 Report control*/ 0x0024, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000024 VT Blk A Alm VT #12 Masking Option*/ 0x0025, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000025 VT Blk A Alm VT #13 Report control*/ 0x0025, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000025 VT Blk A Alm VT #13 Masking Option*/ 0x0026, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000026 VT Blk A Alm VT #14 Report control*/ 0x0026, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000026 VT Blk A Alm VT #14 Masking Option*/ 0x0027, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000027 VT Blk A Alm VT #15 Report control*/ 0x0027, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000027 VT Blk A Alm VT #15 Masking Option*/ 0x0028, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000028 VT Blk A Alm VT #16 Report control*/ 0x0028, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000028 VT Blk A Alm VT #16 Masking Option*/ 0x0029, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x00000029 VT Blk A Alm VT #17 Report control*/ 0x0029, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x00000029 VT Blk A Alm VT #17 Masking Option*/ 0x002a, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000002a VT Blk A Alm VT #18 Report control*/ 0x002a, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x0000002a VT Blk A Alm VT #18 Masking Option*/ 0x002b, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000002b VT Blk A Alm VT #19 Report control*/ 0x002b, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x0000002b VT Blk A Alm VT #19 Masking Option*/ 0x002c, PROV, 0x00ff, 0x0000, SAMP_INTCTRL11_REGS , /*0x0000002c VT Blk A Alm VT #20 Report control*/ 0x002c, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL11_REGS , /*0x0000002c VT Blk A Alm VT #20 Masking Option*/ 0x002d, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000002d VT Blk A Alm VT #21 Report control*/ 0x002d, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000002d VT Blk A Alm VT #21 Masking Option*/ 0x002e, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000002e VT Blk A Alm VT #22 Report control*/ 0x002e, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000002e VT Blk A Alm VT #22 Masking Option*/ 0x002f, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000002f VT Blk A Alm VT #23 Report control*/ 0x002f, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000002f VT Blk A Alm VT #23 Masking Option*/ 0x0030, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000030 VT Blk A Alm VT #24 Report control*/ 0x0030, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000030 VT Blk A Alm VT #24 Masking Option*/ 0x0031, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000031 VT Blk A Alm VT #25 Report control*/ 0x0031, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000031 VT Blk A Alm VT #25 Masking Option*/ 0x0032, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000032 VT Blk A Alm VT #26 Report control*/ 0x0032, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000032 VT Blk A Alm VT #26 Masking Option*/ 0x0033, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000033 VT Blk A Alm VT #27 Report control*/ 0x0033, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000033 VT Blk A Alm VT #27 Masking Option*/ 0x0034, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000034 VT Blk A Alm VT #28 Report control*/ 0x0034, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000034 VT Blk A Alm VT #28 Masking Option*/ 0x0035, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000035 VT Blk B Alm VT #1 Report control*/ 0x0035, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000035 VT Blk B Alm VT #1 Masking Option*/ 0x0036, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000036 VT Blk B Alm VT #2 Report control*/ 0x0036, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000036 VT Blk B Alm VT #2 Masking Option*/ 0x0037, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000037 VT Blk B Alm VT #3 Report control*/ 0x0037, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000037 VT Blk B Alm VT #3 Masking Option*/ 0x0038, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000038 VT Blk B Alm VT #4 Report control*/ 0x0038, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000038 VT Blk B Alm VT #4 Masking Option*/ 0x0039, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000039 VT Blk B Alm VT #5 Report control*/ 0x0039, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000039 VT Blk B Alm VT #5 Masking Option*/ 0x003a, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000003a VT Blk B Alm VT #6 Report control*/ 0x003a, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000003a VT Blk B Alm VT #6 Masking Option*/ 0x003b, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000003b VT Blk B Alm VT #7 Report control*/ 0x003b, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000003b VT Blk B Alm VT #7 Masking Option*/ 0x003c, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000003c VT Blk B Alm VT #8 Report control*/ 0x003c, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000003c VT Blk B Alm VT #8 Masking Option*/ 0x003d, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000003d VT Blk B Alm VT #9 Report control*/ 0x003d, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000003d VT Blk B Alm VT #9 Masking Option*/ 0x003e, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000003e VT Blk B Alm VT #10 Report control*/ 0x003e, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000003e VT Blk B Alm VT #10 Masking Option*/ 0x003f, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000003f VT Blk B Alm VT #11 Report control*/ 0x003f, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000003f VT Blk B Alm VT #11 Masking Option*/ 0x0040, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000040 VT Blk B Alm VT #12 Report control*/ 0x0040, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000040 VT Blk B Alm VT #12 Masking Option*/ 0x0041, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000041 VT Blk B Alm VT #13 Report control*/ 0x0041, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000041 VT Blk B Alm VT #13 Masking Option*/ 0x0042, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000042 VT Blk B Alm VT #14 Report control*/ 0x0042, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000042 VT Blk B Alm VT #14 Masking Option*/ 0x0043, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000043 VT Blk B Alm VT #15 Report control*/ 0x0043, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000043 VT Blk B Alm VT #15 Masking Option*/ 0x0044, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000044 VT Blk B Alm VT #16 Report control*/ 0x0044, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000044 VT Blk B Alm VT #16 Masking Option*/ 0x0045, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000045 VT Blk B Alm VT #17 Report control*/ 0x0045, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000045 VT Blk B Alm VT #17 Masking Option*/ 0x0046, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000046 VT Blk B Alm VT #18 Report control*/ 0x0046, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000046 VT Blk B Alm VT #18 Masking Option*/ 0x0047, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000047 VT Blk B Alm VT #19 Report control*/ 0x0047, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000047 VT Blk B Alm VT #19 Masking Option*/ 0x0048, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000048 VT Blk B Alm VT #20 Report control*/ 0x0048, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000048 VT Blk B Alm VT #20 Masking Option*/ 0x0049, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000049 VT Blk B Alm VT #21 Report control*/ 0x0049, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000049 VT Blk B Alm VT #21 Masking Option*/ 0x004a, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000004a VT Blk B Alm VT #22 Report control*/ 0x004a, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000004a VT Blk B Alm VT #22 Masking Option*/ 0x004b, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000004b VT Blk B Alm VT #23 Report control*/ 0x004b, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000004b VT Blk B Alm VT #23 Masking Option*/ 0x004c, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000004c VT Blk B Alm VT #24 Report control*/ 0x004c, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000004c VT Blk B Alm VT #24 Masking Option*/ 0x004d, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000004d VT Blk B Alm VT #25 Report control*/ 0x004d, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000004d VT Blk B Alm VT #25 Masking Option*/ 0x004e, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000004e VT Blk B Alm VT #26 Report control*/ 0x004e, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000004e VT Blk B Alm VT #26 Masking Option*/ 0x004f, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x0000004f VT Blk B Alm VT #27 Report control*/ 0x004f, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x0000004f VT Blk B Alm VT #27 Masking Option*/ 0x0050, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000050 VT Blk B Alm VT #28 Report control*/ 0x0050, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000050 VT Blk B Alm VT #28 Masking Option*/ 0x0051, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000051 VT Blk C Alm VT #1 Report control*/ 0x0051, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000051 VT Blk C Alm VT #1 Masking Option*/ 0x0052, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000052 VT Blk C Alm VT #2 Report control*/ 0x0052, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000052 VT Blk C Alm VT #2 Masking Option*/ 0x0053, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000053 VT Blk C Alm VT #3 Report control*/ 0x0053, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000053 VT Blk C Alm VT #3 Masking Option*/ 0x0054, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000054 VT Blk C Alm VT #4 Report control*/ 0x0054, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000054 VT Blk C Alm VT #4 Masking Option*/ 0x0055, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000055 VT Blk C Alm VT #5 Report control*/ 0x0055, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000055 VT Blk C Alm VT #5 Masking Option*/ 0x0056, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000056 VT Blk C Alm VT #6 Report control*/ 0x0056, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000056 VT Blk C Alm VT #6 Masking Option*/ 0x0057, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000057 VT Blk C Alm VT #7 Report control*/ 0x0057, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000057 VT Blk C Alm VT #7 Masking Option*/ 0x0058, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000058 VT Blk C Alm VT #8 Report control*/ 0x0058, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000058 VT Blk C Alm VT #8 Masking Option*/ 0x0059, PROV, 0x00ff, 0x0000, SAMP_INTCTRL21_REGS , /*0x00000059 VT Blk C Alm VT #9 Report control*/ 0x0059, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL21_REGS , /*0x00000059 VT Blk C Alm VT #9 Masking Option*/ 0x005a, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x0000005a VT Blk C Alm VT #10 Report control*/ 0x005a, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x0000005a VT Blk C Alm VT #10 Masking Option*/ 0x005b, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x0000005b VT Blk C Alm VT #11 Report control*/ 0x005b, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x0000005b VT Blk C Alm VT #11 Masking Option*/ 0x005c, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x0000005c VT Blk C Alm VT #12 Report control*/ 0x005c, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x0000005c VT Blk C Alm VT #12 Masking Option*/ 0x005d, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x0000005d VT Blk C Alm VT #13 Report control*/ 0x005d, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x0000005d VT Blk C Alm VT #13 Masking Option*/ 0x005e, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x0000005e VT Blk C Alm VT #14 Report control*/ 0x005e, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x0000005e VT Blk C Alm VT #14 Masking Option*/ 0x005f, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x0000005f VT Blk C Alm VT #15 Report control*/ 0x005f, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x0000005f VT Blk C Alm VT #15 Masking Option*/ 0x0060, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x00000060 VT Blk C Alm VT #16 Report control*/ 0x0060, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x00000060 VT Blk C Alm VT #16 Masking Option*/ 0x0061, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x00000061 VT Blk C Alm VT #17 Report control*/ 0x0061, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x00000061 VT Blk C Alm VT #17 Masking Option*/ 0x0062, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x00000062 VT Blk C Alm VT #18 Report control*/ 0x0062, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x00000062 VT Blk C Alm VT #18 Masking Option*/ 0x0063, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x00000063 VT Blk C Alm VT #19 Report control*/ 0x0063, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x00000063 VT Blk C Alm VT #19 Masking Option*/ 0x0064, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x00000064 VT Blk C Alm VT #20 Report control*/ 0x0064, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x00000064 VT Blk C Alm VT #20 Masking Option*/ 0x0065, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x00000065 VT Blk C Alm VT #21 Report control*/ 0x0065, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x00000065 VT Blk C Alm VT #21 Masking Option*/ 0x0066, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x00000066 VT Blk C Alm VT #22 Report control*/ 0x0066, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x00000066 VT Blk C Alm VT #22 Masking Option*/ 0x0067, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x00000067 VT Blk C Alm VT #23 Report control*/ 0x0067, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x00000067 VT Blk C Alm VT #23 Masking Option*/ 0x0068, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x00000068 VT Blk C Alm VT #24 Report control*/ 0x0068, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x00000068 VT Blk C Alm VT #24 Masking Option*/ 0x0069, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x00000069 VT Blk C Alm VT #25 Report control*/ 0x0069, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x00000069 VT Blk C Alm VT #25 Masking Option*/ 0x006a, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x0000006a VT Blk C Alm VT #26 Report control*/ 0x006a, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x0000006a VT Blk C Alm VT #26 Masking Option*/ 0x006b, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x0000006b VT Blk C Alm VT #27 Report control*/ 0x006b, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x0000006b VT Blk C Alm VT #27 Masking Option*/ 0x006c, PROV, 0x00ff, 0x0000, SAMP_INTCTRL31_REGS , /*0x0000006c VT Blk C Alm VT #28 Report control*/ 0x006c, PROV, 0x00ff, 0x00ff, SAMP_INTCTRL31_REGS , /*0x0000006c VT Blk C Alm VT #28 Masking Option*/ }; int vtpa_int_groups [] = { SAMP_INTCTRL11_REGS,SAMP_INTCTRL21_REGS,SAMP_INTCTRL31_REGS, }; int num_vtpa_int_groups = 3; schar vtpa_int_msg[] = "SAMP"; schar vtpa_int_clr_msg[] = " Cleared"; void vtpa_intr_clkint_func(ubyte, ubyte); /* 0x00000000 Clock Sel Interrupt */ void vtpa_intr_strint_func(ubyte, ubyte); /* 0x00000004 STAR I/F Interrupt Summary */ void vtpa_intr_mstint_func(ubyte, ubyte); /* 0x00000008 Master Interrupt Summary */ void vtpa_intr_genichg_func(ubyte, ubyte); /* 0x0000001e Generic Input Change */ void vtpa_intr_tmgint_func(ubyte, ubyte); /* 0x00000102 Timing Interrupt Reg */ void vtpa_intr_in1sum_func(ubyte, ubyte); /* 0x00000158 Star In Int Summary (Gp 1) */ void vtpa_intr_in1dbc_func(ubyte, ubyte); /* 0x00000168 Input D1/D2 Change Interrupt (Gp 1) */ void vtpa_intr_in2sum_func(ubyte, ubyte); /* 0x00000198 Star In Int Summary (Gp 2) */ void vtpa_intr_in2dbc_func(ubyte, ubyte); /* 0x000001a8 Input D1/D2 Change Interrupt (Gp 2) */ void vtpa_intr_in3sum_func(ubyte, ubyte); /* 0x000001d8 Star In Int Summary (Gp 3) */ void vtpa_intr_in3dbc_func(ubyte, ubyte); /* 0x000001e8 Input D1/D2 Change Interrupt (Gp 3) */ void vtpa_intr_ibperr_func(ubyte, ubyte); /* 0x00000220 Inband Parity Error */ void vtpa_intr_stsstat1_func(ubyte, ubyte); /* 0x000002c0 STS PM Status STS #1 */ void vtpa_intr_stsstat2_func(ubyte, ubyte); /* 0x000002c2 STS PM Status STS #2 */ void vtpa_intr_stsstat3_func(ubyte, ubyte); /* 0x000002c4 STS PM Status STS #3 */ void vtpa_intr_stsstat4_func(ubyte, ubyte); /* 0x000002c6 STS PM Status STS #4 */ void vtpa_intr_stsstat5_func(ubyte, ubyte); /* 0x000002c8 STS PM Status STS #5 */ void vtpa_intr_stsstat6_func(ubyte, ubyte); /* 0x000002ca STS PM Status STS #6 */ void vtpa_intr_stsstat7_func(ubyte, ubyte); /* 0x000002cc STS PM Status STS #7 */ void vtpa_intr_stsstat8_func(ubyte, ubyte); /* 0x000002ce STS PM Status STS #8 */ void vtpa_intr_stsstat9_func(ubyte, ubyte); /* 0x000002d0 STS PM Status STS #9 */ void vtpa_intr_stsstat10_func(ubyte, ubyte); /* 0x000002d2 STS PM Status STS #10 */ void vtpa_intr_stsstat11_func(ubyte, ubyte); /* 0x000002d4 STS PM Status STS #11 */ void vtpa_intr_stsstat12_func(ubyte, ubyte); /* 0x000002d6 STS PM Status STS #12 */ void vtpa_intr_vtmfls_func(ubyte, ubyte); /* 0x00000310 VT Multiframe Loss Interrupt */ void vtpa_intr_vtaint1_func(ubyte, ubyte); /* 0x00000400 VT Blk A Alm VT #1 */ void vtpa_intr_vtaint2_func(ubyte, ubyte); /* 0x00000402 VT Blk A Alm VT #2 */ void vtpa_intr_vtaint3_func(ubyte, ubyte); /* 0x00000404 VT Blk A Alm VT #3 */ void vtpa_intr_vtaint4_func(ubyte, ubyte); /* 0x00000406 VT Blk A Alm VT #4 */ void vtpa_intr_vtaint5_func(ubyte, ubyte); /* 0x00000408 VT Blk A Alm VT #5 */ void vtpa_intr_vtaint6_func(ubyte, ubyte); /* 0x0000040a VT Blk A Alm VT #6 */ void vtpa_intr_vtaint7_func(ubyte, ubyte); /* 0x0000040c VT Blk A Alm VT #7 */ void vtpa_intr_vtaint8_func(ubyte, ubyte); /* 0x0000040e VT Blk A Alm VT #8 */ void vtpa_intr_vtaint9_func(ubyte, ubyte); /* 0x00000410 VT Blk A Alm VT #9 */ void vtpa_intr_vtaint10_func(ubyte, ubyte); /* 0x00000412 VT Blk A Alm VT #10 */ void vtpa_intr_vtaint11_func(ubyte, ubyte); /* 0x00000414 VT Blk A Alm VT #11 */ void vtpa_intr_vtaint12_func(ubyte, ubyte); /* 0x00000416 VT Blk A Alm VT #12 */ void vtpa_intr_vtaint13_func(ubyte, ubyte); /* 0x00000418 VT Blk A Alm VT #13 */ void vtpa_intr_vtaint14_func(ubyte, ubyte); /* 0x0000041a VT Blk A Alm VT #14 */ void vtpa_intr_vtaint15_func(ubyte, ubyte); /* 0x0000041c VT Blk A Alm VT #15 */ void vtpa_intr_vtaint16_func(ubyte, ubyte); /* 0x0000041e VT Blk A Alm VT #16 */ void vtpa_intr_vtaint17_func(ubyte, ubyte); /* 0x00000420 VT Blk A Alm VT #17 */ void vtpa_intr_vtaint18_func(ubyte, ubyte); /* 0x00000422 VT Blk A Alm VT #18 */ void vtpa_intr_vtaint19_func(ubyte, ubyte); /* 0x00000424 VT Blk A Alm VT #19 */ void vtpa_intr_vtaint20_func(ubyte, ubyte); /* 0x00000426 VT Blk A Alm VT #20 */ void vtpa_intr_vtaint21_func(ubyte, ubyte); /* 0x00000428 VT Blk A Alm VT #21 */ void vtpa_intr_vtaint22_func(ubyte, ubyte); /* 0x0000042a VT Blk A Alm VT #22 */ void vtpa_intr_vtaint23_func(ubyte, ubyte); /* 0x0000042c VT Blk A Alm VT #23 */ void vtpa_intr_vtaint24_func(ubyte, ubyte); /* 0x0000042e VT Blk A Alm VT #24 */ void vtpa_intr_vtaint25_func(ubyte, ubyte); /* 0x00000430 VT Blk A Alm VT #25 */ void vtpa_intr_vtaint26_func(ubyte, ubyte); /* 0x00000432 VT Blk A Alm VT #26 */ void vtpa_intr_vtaint27_func(ubyte, ubyte); /* 0x00000434 VT Blk A Alm VT #27 */ void vtpa_intr_vtaint28_func(ubyte, ubyte); /* 0x00000436 VT Blk A Alm VT #28 */ void vtpa_intr_vtbint1_func(ubyte, ubyte); /* 0x00000440 VT Blk B Alm VT #1 */ void vtpa_intr_vtbint2_func(ubyte, ubyte); /* 0x00000442 VT Blk B Alm VT #2 */ void vtpa_intr_vtbint3_func(ubyte, ubyte); /* 0x00000444 VT Blk B Alm VT #3 */ void vtpa_intr_vtbint4_func(ubyte, ubyte); /* 0x00000446 VT Blk B Alm VT #4 */ void vtpa_intr_vtbint5_func(ubyte, ubyte); /* 0x00000448 VT Blk B Alm VT #5 */ void vtpa_intr_vtbint6_func(ubyte, ubyte); /* 0x0000044a VT Blk B Alm VT #6 */ void vtpa_intr_vtbint7_func(ubyte, ubyte); /* 0x0000044c VT Blk B Alm VT #7 */ void vtpa_intr_vtbint8_func(ubyte, ubyte); /* 0x0000044e VT Blk B Alm VT #8 */ void vtpa_intr_vtbint9_func(ubyte, ubyte); /* 0x00000450 VT Blk B Alm VT #9 */ void vtpa_intr_vtbint10_func(ubyte, ubyte); /* 0x00000452 VT Blk B Alm VT #10 */ void vtpa_intr_vtbint11_func(ubyte, ubyte); /* 0x00000454 VT Blk B Alm VT #11 */ void vtpa_intr_vtbint12_func(ubyte, ubyte); /* 0x00000456 VT Blk B Alm VT #12 */ void vtpa_intr_vtbint13_func(ubyte, ubyte); /* 0x00000458 VT Blk B Alm VT #13 */ void vtpa_intr_vtbint14_func(ubyte, ubyte); /* 0x0000045a VT Blk B Alm VT #14 */ void vtpa_intr_vtbint15_func(ubyte, ubyte); /* 0x0000045c VT Blk B Alm VT #15 */ void vtpa_intr_vtbint16_func(ubyte, ubyte); /* 0x0000045e VT Blk B Alm VT #16 */ void vtpa_intr_vtbint17_func(ubyte, ubyte); /* 0x00000460 VT Blk B Alm VT #17 */ void vtpa_intr_vtbint18_func(ubyte, ubyte); /* 0x00000462 VT Blk B Alm VT #18 */ void vtpa_intr_vtbint19_func(ubyte, ubyte); /* 0x00000464 VT Blk B Alm VT #19 */ void vtpa_intr_vtbint20_func(ubyte, ubyte); /* 0x00000466 VT Blk B Alm VT #20 */ void vtpa_intr_vtbint21_func(ubyte, ubyte); /* 0x00000468 VT Blk B Alm VT #21 */ void vtpa_intr_vtbint22_func(ubyte, ubyte); /* 0x0000046a VT Blk B Alm VT #22 */ void vtpa_intr_vtbint23_func(ubyte, ubyte); /* 0x0000046c VT Blk B Alm VT #23 */ void vtpa_intr_vtbint24_func(ubyte, ubyte); /* 0x0000046e VT Blk B Alm VT #24 */ void vtpa_intr_vtbint25_func(ubyte, ubyte); /* 0x00000470 VT Blk B Alm VT #25 */ void vtpa_intr_vtbint26_func(ubyte, ubyte); /* 0x00000472 VT Blk B Alm VT #26 */ void vtpa_intr_vtbint27_func(ubyte, ubyte); /* 0x00000474 VT Blk B Alm VT #27 */ void vtpa_intr_vtbint28_func(ubyte, ubyte); /* 0x00000476 VT Blk B Alm VT #28 */ void vtpa_intr_vtcint1_func(ubyte, ubyte); /* 0x00000480 VT Blk C Alm VT #1 */ void vtpa_intr_vtcint2_func(ubyte, ubyte); /* 0x00000482 VT Blk C Alm VT #2 */ void vtpa_intr_vtcint3_func(ubyte, ubyte); /* 0x00000484 VT Blk C Alm VT #3 */ void vtpa_intr_vtcint4_func(ubyte, ubyte); /* 0x00000486 VT Blk C Alm VT #4 */ void vtpa_intr_vtcint5_func(ubyte, ubyte); /* 0x00000488 VT Blk C Alm VT #5 */ void vtpa_intr_vtcint6_func(ubyte, ubyte); /* 0x0000048a VT Blk C Alm VT #6 */ void vtpa_intr_vtcint7_func(ubyte, ubyte); /* 0x0000048c VT Blk C Alm VT #7 */ void vtpa_intr_vtcint8_func(ubyte, ubyte); /* 0x0000048e VT Blk C Alm VT #8 */ void vtpa_intr_vtcint9_func(ubyte, ubyte); /* 0x00000490 VT Blk C Alm VT #9 */ void vtpa_intr_vtcint10_func(ubyte, ubyte); /* 0x00000492 VT Blk C Alm VT #10 */ void vtpa_intr_vtcint11_func(ubyte, ubyte); /* 0x00000494 VT Blk C Alm VT #11 */ void vtpa_intr_vtcint12_func(ubyte, ubyte); /* 0x00000496 VT Blk C Alm VT #12 */ void vtpa_intr_vtcint13_func(ubyte, ubyte); /* 0x00000498 VT Blk C Alm VT #13 */ void vtpa_intr_vtcint14_func(ubyte, ubyte); /* 0x0000049a VT Blk C Alm VT #14 */ void vtpa_intr_vtcint15_func(ubyte, ubyte); /* 0x0000049c VT Blk C Alm VT #15 */ void vtpa_intr_vtcint16_func(ubyte, ubyte); /* 0x0000049e VT Blk C Alm VT #16 */ void vtpa_intr_vtcint17_func(ubyte, ubyte); /* 0x000004a0 VT Blk C Alm VT #17 */ void vtpa_intr_vtcint18_func(ubyte, ubyte); /* 0x000004a2 VT Blk C Alm VT #18 */ void vtpa_intr_vtcint19_func(ubyte, ubyte); /* 0x000004a4 VT Blk C Alm VT #19 */ void vtpa_intr_vtcint20_func(ubyte, ubyte); /* 0x000004a6 VT Blk C Alm VT #20 */ void vtpa_intr_vtcint21_func(ubyte, ubyte); /* 0x000004a8 VT Blk C Alm VT #21 */ void vtpa_intr_vtcint22_func(ubyte, ubyte); /* 0x000004aa VT Blk C Alm VT #22 */ void vtpa_intr_vtcint23_func(ubyte, ubyte); /* 0x000004ac VT Blk C Alm VT #23 */ void vtpa_intr_vtcint24_func(ubyte, ubyte); /* 0x000004ae VT Blk C Alm VT #24 */ void vtpa_intr_vtcint25_func(ubyte, ubyte); /* 0x000004b0 VT Blk C Alm VT #25 */ void vtpa_intr_vtcint26_func(ubyte, ubyte); /* 0x000004b2 VT Blk C Alm VT #26 */ void vtpa_intr_vtcint27_func(ubyte, ubyte); /* 0x000004b4 VT Blk C Alm VT #27 */ void vtpa_intr_vtcint28_func(ubyte, ubyte); /* 0x000004b6 VT Blk C Alm VT #28 */ struct intr_struct vtpa_interrupts[] = { /* offset, rpt value, msk value, mask_offset, func ptr */ 0x0000, 0x0000, 0x000f, 0x0002, vtpa_intr_clkint_func, 0x0004, 0x0000, 0x0007, 0x0002, vtpa_intr_strint_func, 0x0008, 0x0000, 0x01ff, 0x000a, vtpa_intr_mstint_func, 0x001e, 0x0000, 0x00ff, 0x0020, vtpa_intr_genichg_func, 0x0102, 0x0000, 0x001f, 0x0104, vtpa_intr_tmgint_func, 0x0158, 0x0000, 0x001f, 0x0156, vtpa_intr_in1sum_func, 0x0168, 0x0000, 0x000f, 0x016a, vtpa_intr_in1dbc_func, 0x0198, 0x0000, 0x001f, 0x0196, vtpa_intr_in2sum_func, 0x01a8, 0x0000, 0x000f, 0x01aa, vtpa_intr_in2dbc_func, 0x01d8, 0x0000, 0x001f, 0x01d6, vtpa_intr_in3sum_func, 0x01e8, 0x0000, 0x000f, 0x01ea, vtpa_intr_in3dbc_func, 0x0220, 0x0000, 0x0fff, 0x0222, vtpa_intr_ibperr_func, 0x02c0, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat1_func, 0x02c2, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat2_func, 0x02c4, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat3_func, 0x02c6, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat4_func, 0x02c8, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat5_func, 0x02ca, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat6_func, 0x02cc, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat7_func, 0x02ce, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat8_func, 0x02d0, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat9_func, 0x02d2, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat10_func, 0x02d4, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat11_func, 0x02d6, 0x0000, 0x001f, 0x02e0, vtpa_intr_stsstat12_func, 0x0310, 0x0000, 0x0007, 0x0312, vtpa_intr_vtmfls_func, 0x0400, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint1_func, 0x0402, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint2_func, 0x0404, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint3_func, 0x0406, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint4_func, 0x0408, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint5_func, 0x040a, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint6_func, 0x040c, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint7_func, 0x040e, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint8_func, 0x0410, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint9_func, 0x0412, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint10_func, 0x0414, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint11_func, 0x0416, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint12_func, 0x0418, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint13_func, 0x041a, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint14_func, 0x041c, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint15_func, 0x041e, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint16_func, 0x0420, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint17_func, 0x0422, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint18_func, 0x0424, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint19_func, 0x0426, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint20_func, 0x0428, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint21_func, 0x042a, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint22_func, 0x042c, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint23_func, 0x042e, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint24_func, 0x0430, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint25_func, 0x0432, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint26_func, 0x0434, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint27_func, 0x0436, 0x0000, 0x00ff, 0x0700, vtpa_intr_vtaint28_func, 0x0440, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint1_func, 0x0442, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint2_func, 0x0444, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint3_func, 0x0446, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint4_func, 0x0448, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint5_func, 0x044a, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint6_func, 0x044c, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint7_func, 0x044e, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint8_func, 0x0450, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint9_func, 0x0452, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint10_func, 0x0454, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint11_func, 0x0456, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint12_func, 0x0458, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint13_func, 0x045a, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint14_func, 0x045c, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint15_func, 0x045e, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint16_func, 0x0460, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint17_func, 0x0462, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint18_func, 0x0464, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint19_func, 0x0466, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint20_func, 0x0468, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint21_func, 0x046a, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint22_func, 0x046c, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint23_func, 0x046e, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint24_func, 0x0470, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint25_func, 0x0472, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint26_func, 0x0474, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint27_func, 0x0476, 0x0000, 0x00ff, 0x0740, vtpa_intr_vtbint28_func, 0x0480, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint1_func, 0x0482, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint2_func, 0x0484, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint3_func, 0x0486, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint4_func, 0x0488, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint5_func, 0x048a, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint6_func, 0x048c, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint7_func, 0x048e, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint8_func, 0x0490, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint9_func, 0x0492, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint10_func, 0x0494, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint11_func, 0x0496, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint12_func, 0x0498, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint13_func, 0x049a, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint14_func, 0x049c, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint15_func, 0x049e, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint16_func, 0x04a0, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint17_func, 0x04a2, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint18_func, 0x04a4, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint19_func, 0x04a6, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint20_func, 0x04a8, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint21_func, 0x04aa, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint22_func, 0x04ac, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint23_func, 0x04ae, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint24_func, 0x04b0, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint25_func, 0x04b2, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint26_func, 0x04b4, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint27_func, 0x04b6, 0x0000, 0x00ff, 0x0780, vtpa_intr_vtcint28_func, NULL }; void vtpa_intr_clkint_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_strint_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_mstint_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_genichg_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_tmgint_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_in1sum_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_in1dbc_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_in2sum_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_in2dbc_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_in3sum_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_in3dbc_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_ibperr_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat1_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat2_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat3_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat4_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat5_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat6_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat7_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat8_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat9_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat10_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat11_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_stsstat12_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtmfls_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint1_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint2_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint3_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint4_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint5_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint6_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint7_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint8_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint9_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint10_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint11_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint12_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint13_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint14_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint15_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint16_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint17_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint18_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint19_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint20_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint21_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint22_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint23_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint24_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint25_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint26_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint27_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtaint28_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint1_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint2_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint3_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint4_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint5_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint6_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint7_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint8_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint9_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint10_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint11_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint12_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint13_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint14_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint15_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint16_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint17_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint18_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint19_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint20_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint21_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint22_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint23_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint24_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint25_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint26_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint27_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtbint28_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint1_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint2_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint3_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint4_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint5_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint6_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint7_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint8_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint9_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint10_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint11_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint12_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint13_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint14_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint15_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint16_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint17_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint18_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint19_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint20_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint21_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint22_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint23_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint24_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint25_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint26_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint27_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ void vtpa_intr_vtcint28_func(ubyte bit, ubyte event) { } /* interrupt callback funtion*/ uword vtpa_prev_alarm[NUM_SAMPS_ON_PBA][NUM_SAMP_ALARM_GROUPS]; struct asic_info_struct { long *asic_list; int num_regs; char reg_width; int num_asic_int_groups; int *int_groups; struct asic_reg_struct *asic; struct asic_config_num *asic_configs; struct intr_struct *asic_interrupts; ubyte *alive; }; struct asic_info_struct vtpa_info; void init_vtpa_info() { vtpa_info.asic_list = vtpa_base; vtpa_info.num_regs = NUM_SAMP_REGS; vtpa_info.reg_width = SAMP_REG_WIDTH; vtpa_info.num_asic_int_groups = num_vtpa_int_groups; vtpa_info.int_groups = vtpa_int_groups; vtpa_info.asic = vtpa; vtpa_info.asic_configs = vtpa_configs; vtpa_info.asic_interrupts = vtpa_interrupts; vtpa_info.alive = vtpa_alive; } static unsigned int common_find_index(struct asic_info_struct *, unsigned int); /***************************************************************************/ /* initialize all interrupt shadows, so we know what happened from the */ /* last time the interrupts were read */ void vtpa_init_ints(ubyte first_vtpa_no, ubyte last_vtpa_no) { data_type x,a; for(a=first_vtpa_no; a <= last_vtpa_no; a++) { for(x = 0; x < NUM_SAMP_ALARM_GROUPS; x++) vtpa_prev_alarm[a][x] = 0x0000; /* old_inslot[a] = 0x0000; for use on LIFs to keep track of the old status of the LDR slots*/ } } /***************************************************************************/ /* Read the new alarms and compare to the prev_alarm to see if any alarms changed state. If they did build a message but only report it if the report_mask value says we should. This routine uses the CAM message format to save bandwidth for reporting interrupt changes. */ void vtpa_ints(ubyte first_vtpa, ubyte last_vtpa_no) { data_type bit, disable_mask, enable_mask, alarm_group, alarm_changes, bit_to_test, inslot_done; char message[81]; char vtpa_no; data_type curr_alarm; char *ptr; data_type ignore_int, mask, save_mask; /* limit this task to at least once every 500 usec or more */ if ( ( *timer1 - bkgnd_time ) < BKGND_TIMEOUT ) return; bkgnd_time = *timer1; init_vtpa_info(); /* for each vtpa */ for(vtpa_no = first_vtpa; vtpa_no <= last_vtpa_no; vtpa_no++) { inslot_done = 0; /* for each alarm in the vtpa */ for(alarm_group = 0; alarm_group < NUM_SAMP_ALARM_GROUPS; alarm_group++) { curr_alarm = READ_ASIC(vtpa_base[vtpa_no], vtpa_info.asic_interrupts[alarm_group].offset, vtpa[common_find_index(&vtpa_info, vtpa_info.asic_interrupts[alarm_group].offset)].mask); /* see what changed form last time */ alarm_changes = curr_alarm ^ vtpa_prev_alarm[vtpa_no][alarm_group]; vtpa_prev_alarm[vtpa_no][alarm_group] = curr_alarm; if(alarm_changes != 0) { /* initialize the walking 1 bit pattern to check each alarm bit */ bit_to_test = 0x0001; if(vtpa_info.asic_interrupts[alarm_group].masked_by_offset == 0xffffffff) mask = 0x0000; else mask = READ_ASIC(vtpa_base[vtpa_no], vtpa[common_find_index(&vtpa_info, vtpa_info.asic_interrupts[alarm_group].masked_by_offset)].offset, vtpa[common_find_index(&vtpa_info, vtpa_info.asic_interrupts[alarm_group].masked_by_offset)].mask); save_mask = mask; for(bit = 0; bit < SAMP_REG_WIDTH; bit++) { ignore_int = bit_to_test & mask; if((alarm_changes & bit_to_test) && !(ignore_int)) /* if bit changed and mask bit clear */ { ptr = (char *) message; *ptr++ = 0xff; *ptr++ = vtpa_no; *ptr++ = alarm_group; *ptr++ = bit; if(curr_alarm & bit_to_test) /* if bit is a 1 then alarm occurred */ { *ptr++ = 1; /* interrupt occurred */ vtpa_interrupts[alarm_group].intr_function(bit,ASIC_INTR); if(vtpa_interrupts[alarm_group].mask_option_value & bit_to_test) mask |= bit_to_test; } else /* alarm cleared */ { *ptr++ = 0; /* interrupt Cleared */ vtpa_interrupts[alarm_group].intr_function(bit,INTR_CLR); /* clear mask for this bit */ if(!(vtpa_interrupts[alarm_group].mask_option_value & bit_to_test)) mask &= (data_type)~bit_to_test; } *ptr++ = 0; /* open for future use */ /* now only send this message if we are supposed to send it */ if(vtpa_interrupts[alarm_group].rptctrl_value & bit_to_test) send_new_cam( message ); } /* if change and not ignore */ bit_to_test <<= 1; /* shift bit mask */ } /* bit loop */ if((mask ^ save_mask) && ( vtpa_info.asic_interrupts[alarm_group].masked_by_offset != 0xffffffff)) { WRITE_ASIC(vtpa_base[vtpa_no], vtpa[common_find_index( &vtpa_info,vtpa_info.asic_interrupts[alarm_group].masked_by_offset)].offset, mask); } } /* alarm change */ } } /* end for vtpa_no */ } #include "asic_fnc.h" /* functions common to all asics */ /***************************************************************************/ void dflt_vtpa_prov_cmd(struct asic_info_struct *asic_info, ubyte asic_no ) { init_vtpa_info(); put_byte( ASIC_DFLT_FUNC ); if(common_dflt_asic(asic_info, asic_no)) put_byte( SUCCESS ); else put_byte( NO_DVC ); } /***************************************************************************/ void vtpa_cmd() { ubyte cfg; ubyte cmd; init_vtpa_info(); if ( get_byte( &cmd ) && (curr_packet->instance <= NUM_SAMPS_ON_PBA) ) { switch ( cmd ) { case ASIC_DFLT_FUNC: dflt_vtpa_prov_cmd(&vtpa_info, curr_packet->instance ); /* Load shadow with dflts (Ints on) */ break; case ASIC_INFO_FUNC: asic_info_cmd(&vtpa_info); /* Print out asic info */ break; case ASIC_CFG_FUNC: get_byte(&cfg); cfg_asic_cmd(&vtpa_info, cfg, curr_packet->instance); break; default: put_byte( cmd ); put_byte( PARAM_ERR ); break; } /* of switch for all cmds */ } else { put_byte( cmd ); put_byte( PARAM_ERR ); } } /***************************************************************************/ void vtpa_regset_cmd() { ubyte cfg; ubyte group; ubyte cmd; init_vtpa_info(); if(get_byte( &cmd ) && get_byte( &group ) && (group <= SAMP_LAST_REGS) && (curr_packet->instance <= NUM_SAMPS_ON_PBA) ) { switch ( cmd ) { case ASIC_GETPROV_FUNC: common_get_asic_prov_cmd( &vtpa_info, group, curr_packet->instance, TRUE ); /* Send header to usr_int */ break; case ASIC_SETPROV_FUNC: set_asic_prov_cmd( &vtpa_info, group, curr_packet->instance ); break; default: put_byte( cmd ); put_byte( group ); put_byte( PARAM_ERR ); break; } /* of switch for all cmds */ } else { put_byte( cmd ); put_byte( group ); put_byte( PARAM_ERR ); } } static void (*vtpa_func_list[2])() = { vtpa_regset_cmd, /* RegSet Operations */ vtpa_cmd /* All others */ }; struct funct_table vtpa_functs = { 2, vtpa_func_list }; /****************************************************************************/ void send_vi_byte() { } /****************************************************************************/ /****************************************************************************/ void send_vi_buffer( chan, buff ) int chan; /* Chan To Transmit Out */ struct vi_buffer *buff; /* Data to Transmit */ { } /****************************************************************************/ /* SBI_LINK( 0 ); */ /* End of file */